From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 93C0EC4332F for ; Tue, 29 Nov 2022 08:32:44 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230526AbiK2Icn (ORCPT ); Tue, 29 Nov 2022 03:32:43 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39966 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231151AbiK2Ibx (ORCPT ); Tue, 29 Nov 2022 03:31:53 -0500 Received: from mail.skyhub.de (mail.skyhub.de [IPv6:2a01:4f8:190:11c2::b:1457]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6B28B58038 for ; Tue, 29 Nov 2022 00:31:25 -0800 (PST) Received: from zn.tnic (p5de8e9fe.dip0.t-ipconnect.de [93.232.233.254]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.skyhub.de (SuperMail on ZX Spectrum 128k) with ESMTPSA id 120E91EC04AD; Tue, 29 Nov 2022 09:31:22 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=alien8.de; s=dkim; t=1669710682; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:in-reply-to:in-reply-to: references:references; bh=c2uLthRh1cekqoux6NKDaUFI7tnAo+8/uewFZFHwfUw=; b=jrdvWei+zrZRNks1rtZP6RnET0S8IR3zKlLvTMSkQI3RCmaQjJjieWBA1wv9HTWgpw5jfk HaRcPKPWBACEOplTeXsGcQhXIUCE5IdiNX9TFCFuFDUaGPJnv/UHvupf0ZPuleOCs1pj2z n3VYubTHueFDOsfMz1kSgc1jYFekbUY= Date: Tue, 29 Nov 2022 09:31:17 +0100 From: Borislav Petkov To: Uros Bizjak Cc: x86@kernel.org, linux-kernel@vger.kernel.org, Thomas Gleixner , Ingo Molnar , Dave Hansen , "H. Peter Anvin" Subject: Re: [PATCH] x86/boot: Remove x86_32 PIC using ebx workaround Message-ID: References: <20221104124546.196077-1-ubizjak@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline In-Reply-To: Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, Nov 29, 2022 at 08:39:23AM +0100, Uros Bizjak wrote: > On Mon, Nov 28, 2022 at 11:20 PM Borislav Petkov wrote: > > > > On Fri, Nov 04, 2022 at 01:45:46PM +0100, Uros Bizjak wrote: > > > Current minimum required version of GCC is version 5.1 which allows > > > reuse of PIC hard register on x86/x86-64 targets [1]. Remove > > > obsolete workaround that was needed for earlier GCC versions. > > > > > > [1] https://gcc.gnu.org/gcc-5/changes.html > > > > Thanks for the doc pointer. > > > > Lemme see if I understand this commit message correctly: > > > > SysV i386 ABI says that %ebx is used as the base reg in PIC. gcc 5 and > > newer can handle all possible cases properly where inline asm could > > clobber the PIC reg. I.e., it is able to deal with the "=b" constraint > > where an insn can overwrite %ebx and it'll push and pop around that > > statement. > > gcc-5 considers PIC register as a pseudo-register and reloads it So not a "hard" register as you say above? > x86_64 does not use PIC register for small code models. Also, it uses > %r15 instead of %rbx for PIC register, so the removed workaround > applies only to x86_32. Let's see: arch/x86/Makefile: # Never want PIC in a 32-bit kernel, prevent breakage with GCC built # with nonstandard options KBUILD_CFLAGS += -fno-pic $ gcc -Wp,-MMD,arch/x86/boot/.cpuflags.o.d ... -fno-pic ... -D__KBUILD_MODNAME=kmod_cpuflags -c -o arch/x86/boot/cpuflags.o arch/x86/boot/cpuflags.c So this workaround applies to nothing, I'd say. :) -- Regards/Gruss, Boris. https://people.kernel.org/tglx/notes-about-netiquette