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From: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
To: "Dixit, Ashutosh" <ashutosh.dixit@intel.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH] drm/i915/mtl: Add support for 32 bit OAG formats in MTL
Date: Wed, 30 Nov 2022 15:39:14 -0800	[thread overview]
Message-ID: <Y4fpomJ1Q3mkCOGc@unerlige-ril> (raw)
In-Reply-To: <8735a042ub.wl-ashutosh.dixit@intel.com>

On Wed, Nov 30, 2022 at 12:14:20PM -0800, Dixit, Ashutosh wrote:
>On Wed, 30 Nov 2022 12:00:57 -0800, Umesh Nerlige Ramappa wrote:
>>
>> On Tue, Nov 29, 2022 at 05:51:13PM -0800, Dixit, Ashutosh wrote:
>> > On Mon, 28 Nov 2022 17:21:46 -0800, Umesh Nerlige Ramappa wrote:
>> >>
>> >> +/*
>> >> + * Ref: 14010536224:
>> >> + * 0x20cc is repurposed on MTL, so use a separate array for MTL.
>> >
>> > Wondering if it was WAIT_FOR_RC6_EXIT (seen in gen12_oa_mux_regs) which
>> > moved elsewhere and if that needs to be added to the array below too?
>>
>> WAIT_FOR_RC6_EXIT (0x20cc) moved elsewhere so it should be "removed" from
>> mtl oa mux array.
>
>What I was saying was let's say WAIT_FOR_RC6_EXIT moved to 0xc0ffee so now
>should 0xc0ffee be added to mtl_oa_mux_regs?

oh, sorry, I misread that.

I looked for WAIT_FOR_RC6_EXIT in the bspec and did not find it defined 
for MTL, so it's dropped completely. If you could confirm, that would be 
great.

>
>>
>> >
>> >> + */
>> >> +static const struct i915_range mtl_oa_mux_regs[] = {
>> >> +	{ .start = 0x0d00, .end = 0x0d04 },	/* RPM_CONFIG[0-1] */
>> >> +	{ .start = 0x0d0c, .end = 0x0d2c },	/* NOA_CONFIG[0-8] */
>> >> +	{ .start = 0x9840, .end = 0x9840 },	/* GDT_CHICKEN_BITS */
>> >> +	{ .start = 0x9884, .end = 0x9888 },	/* NOA_WRITE */
>> >> +};
>> >> +
>> >>  static bool gen7_is_valid_b_counter_addr(struct i915_perf *perf, u32 addr)
>> >>  {
>> >>	return reg_in_range_table(addr, gen7_oa_b_counters);
>> >> @@ -4349,7 +4372,10 @@ static bool xehp_is_valid_b_counter_addr(struct i915_perf *perf, u32 addr)
>> >>
>> >>  static bool gen12_is_valid_mux_addr(struct i915_perf *perf, u32 addr)
>> >>  {
>> >> -	return reg_in_range_table(addr, gen12_oa_mux_regs);
>> >> +	if (IS_METEORLAKE(perf->i915))
>> >> +		return reg_in_range_table(addr, mtl_oa_mux_regs);
>> >> +	else
>> >> +		return reg_in_range_table(addr, gen12_oa_mux_regs);
>> >
>> > But otherwise this is:
>> >
>> > Reviewed-by: Ashutosh Dixit <ashutosh.dixit@intel.com>
>>
>> I will break them into separate patches though. If the diff is identical, I
>> will carry over your R-b on the split patches. Please let me know if that's
>> a concern.
>
>No I can quickly review again anyway.

got it, will not add the R-bs.

Thanks,
Umesh

>
>> > If you decide to split the patches, please add my R-b on all the split patches.
>
>Thanks.
>--
>Ashutosh

      reply	other threads:[~2022-11-30 23:39 UTC|newest]

Thread overview: 11+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-11-29  1:21 [Intel-gfx] [PATCH] drm/i915/mtl: Add support for 32 bit OAG formats in MTL Umesh Nerlige Ramappa
2022-11-29  2:20 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for " Patchwork
2022-11-29  2:45 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
2022-11-29  7:15 ` [Intel-gfx] [PATCH] " Lucas De Marchi
2022-11-29 18:40   ` Umesh Nerlige Ramappa
2022-11-30  1:17 ` Dixit, Ashutosh
2022-11-30  1:47   ` Dixit, Ashutosh
2022-11-30  1:51 ` Dixit, Ashutosh
2022-11-30 20:00   ` Umesh Nerlige Ramappa
2022-11-30 20:14     ` Dixit, Ashutosh
2022-11-30 23:39       ` Umesh Nerlige Ramappa [this message]

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