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From: Piergiorgio Beruto <piergiorgio.beruto@gmail.com>
To: Andrew Lunn <andrew@lunn.ch>
Cc: Kurt Kanzenbach <kurt@linutronix.de>,
	Jakub Kicinski <kuba@kernel.org>,
	netdev@vger.kernel.org, peppe.cavallaro@st.com,
	Voon Weifeng <weifeng.voon@intel.com>,
	Rayagond Kokatanur <rayagond@vayavyalabs.com>,
	Jose Abreu <Jose.Abreu@synopsys.com>,
	Antonio Borneo <antonio.borneo@st.com>,
	Tan Tee Min <tee.min.tan@intel.com>
Subject: Re: [PATCH net] stmmac: fix potential division by 0
Date: Thu, 8 Dec 2022 10:27:56 +0100	[thread overview]
Message-ID: <Y5GuHEn161H35/xZ@gvm01> (raw)
In-Reply-To: <Y5EvKciMg3Nkj8ln@lunn.ch>

> > 
> > Here's the Altera manual:
> > 
> >  https://www.intel.com/content/www/us/en/docs/programmable/683126/21-2/functional-description-of-the-emac.html
> > 
> > Table 183 shows the minimum PTP frequencies and also states "Therefore,
> > a higher PTP clock frequency gives better system performance.".
> > 
> > So, I'd say using a clock of 2.5MHz seems possible, but will result in
> > suboptimal precision.
> 
> Thanks for the info. So i seems like the correct fix is to camp to
> 0xff, rather than mask with 0xff.
Andrew, given your comment, do you wish me to re-post the patch with
this fix? Or wait for more feedback first?

Thanks,
Piergiorgio

  reply	other threads:[~2022-12-08  9:27 UTC|newest]

Thread overview: 11+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-12-01  0:37 [PATCH net] stmmac: fix potential division by 0 Piergiorgio Beruto
2022-12-01  1:39 ` Andrew Lunn
2022-12-01 10:24   ` Piergiorgio Beruto
2022-12-01 14:49     ` Andrew Lunn
2022-12-02  8:26       ` Piergiorgio Beruto
2022-12-07  2:28       ` Jakub Kicinski
2022-12-07 13:48         ` Andrew Lunn
2022-12-07 14:50           ` Kurt Kanzenbach
2022-12-08  0:26             ` Andrew Lunn
2022-12-08  9:27               ` Piergiorgio Beruto [this message]
2022-12-10 10:50                 ` Andrew Lunn

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