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[34.168.104.7]) by smtp.gmail.com with ESMTPSA id y10-20020aa793ca000000b0057555d35f79sm1614631pff.101.2022.12.09.12.45.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 09 Dec 2022 12:45:04 -0800 (PST) Date: Fri, 9 Dec 2022 20:45:01 +0000 From: Sean Christopherson To: Oliver Upton Subject: Re: [PATCH v2 4/7] KVM: selftests: Correctly initialize the VA space for TTBR0_EL1 Message-ID: References: <20221209015307.1781352-1-oliver.upton@linux.dev> <20221209015307.1781352-5-oliver.upton@linux.dev> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20221209015307.1781352-5-oliver.upton@linux.dev> Cc: kvm@vger.kernel.org, Marc Zyngier , linux-kernel@vger.kernel.org, linux-kselftest@vger.kernel.org, kvmarm@lists.linux.dev, Paolo Bonzini , Shuah Khan , kvmarm@lists.cs.columbia.edu, linux-arm-kernel@lists.infradead.org X-BeenThere: kvmarm@lists.cs.columbia.edu X-Mailman-Version: 2.1.14 Precedence: list List-Id: Where KVM/ARM decisions are made List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Errors-To: kvmarm-bounces@lists.cs.columbia.edu Sender: kvmarm-bounces@lists.cs.columbia.edu On Fri, Dec 09, 2022, Oliver Upton wrote: > An interesting feature of the Arm architecture is that the stage-1 MMU > supports two distinct VA regions, controlled by TTBR{0,1}_EL1. As KVM > selftests on arm64 only uses TTBR0_EL1, the VA space is constrained to > [0, 2^(va_bits)). This is different from other architectures that > allow for addressing low and high regions of the VA space from a single > page table. > > KVM selftests' VA space allocator presumes the valid address range is > split between low and high memory based the MSB, which of course is a > poor match for arm64's TTBR0 region. > > Add a helper that correctly handles both addressing schemes with a > comment describing each. > > Signed-off-by: Oliver Upton > --- Thanks much! Looks awesome, especially the comment! Reviewed-by: Sean Christopherson > .../selftests/kvm/include/kvm_util_base.h | 1 + > tools/testing/selftests/kvm/lib/kvm_util.c | 49 ++++++++++++++++--- > 2 files changed, 44 insertions(+), 6 deletions(-) > > diff --git a/tools/testing/selftests/kvm/include/kvm_util_base.h b/tools/testing/selftests/kvm/include/kvm_util_base.h > index 6cd86da698b3..b193863d754f 100644 > --- a/tools/testing/selftests/kvm/include/kvm_util_base.h > +++ b/tools/testing/selftests/kvm/include/kvm_util_base.h > @@ -103,6 +103,7 @@ struct kvm_vm { > struct sparsebit *vpages_mapped; > bool has_irqchip; > bool pgd_created; > + bool has_split_va_space; > vm_paddr_t ucall_mmio_addr; > vm_paddr_t pgd; > vm_vaddr_t gdt; > diff --git a/tools/testing/selftests/kvm/lib/kvm_util.c b/tools/testing/selftests/kvm/lib/kvm_util.c > index a256ec67aff6..53d15f32f220 100644 > --- a/tools/testing/selftests/kvm/lib/kvm_util.c > +++ b/tools/testing/selftests/kvm/lib/kvm_util.c > @@ -186,6 +186,43 @@ const struct vm_guest_mode_params vm_guest_mode_params[] = { > _Static_assert(sizeof(vm_guest_mode_params)/sizeof(struct vm_guest_mode_params) == NUM_VM_MODES, > "Missing new mode params?"); > > +/* > + * Initializes vm->vpages_valid to match the canonical VA space of the > + * architecture. > + * > + * Most architectures split the range addressed by a single page table into a > + * low and high region based on the MSB of the VA. On architectures with this > + * behavior the VA region spans [0, 2^(va_bits - 1)), [-(2^(va_bits - 1), -1]. > + * > + * arm64 is a bit different from the rest of the crowd, as the low and high > + * regions of the VA space are addressed by distinct paging structures > + * (TTBR{0,1}_EL1). Oooh, they're different CR3s in x86 terminology? _______________________________________________ kvmarm mailing list kvmarm@lists.cs.columbia.edu https://lists.cs.columbia.edu/mailman/listinfo/kvmarm From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-pl1-f182.google.com (mail-pl1-f182.google.com [209.85.214.182]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B1EA93214 for ; Fri, 9 Dec 2022 20:45:05 +0000 (UTC) Received: by mail-pl1-f182.google.com with SMTP id s7so6102006plk.5 for ; Fri, 09 Dec 2022 12:45:05 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20210112; h=in-reply-to:content-disposition:mime-version:references:message-id :subject:cc:to:from:date:from:to:cc:subject:date:message-id:reply-to; bh=vrO0N2BhoytOAhhhHfUhdN91u6TruVaipT5ISV1vaYc=; b=f95FMmTEKSCikEYcOfIHQeZ11wft/M7xtxOLWqo9ddBFll+PEIhNuP8Altnit2pg7l zyRhiE+JRDfj5dB8/WxDXf1drX13fZ1eOh7rba0AIhbehJO0Y9D2Isb+V0FtO1vE8xtB hYMCbXb+6k8JyDHQhnThQvX/+T5zbEXkZxYWQBSqRWCBdOVJmssGwx1Y5IXZJw/6XRzs S3ZdcDYHIQuWdKlJwLHVsg5FbzwD0u0eYrShli67IQw7Q2mlLjgxmxsG0ncnWSJMMZVg KepJ3JyFSc3873pExBYAY27kO9Gx8PluA0Mbdjh+rOeLvfI90C98illSL1VVYvLRtJsW Xzfw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=in-reply-to:content-disposition:mime-version:references:message-id :subject:cc:to:from:date:x-gm-message-state:from:to:cc:subject:date :message-id:reply-to; bh=vrO0N2BhoytOAhhhHfUhdN91u6TruVaipT5ISV1vaYc=; b=SJYkg+QRqEUlf5d7t+uaQuZ1DBcLfL1MAFzrkn162S1heCg6q3tuneESwSu//SvCbP xD5TYqslNw5Rv1OJgEgorsLr/yBntr0IwO1vnSlQmdoJxXAcILeRL1TsGv8dW49Mb9fK z5n4TSEbjeXdJPXnp+m6Sspj43cOMMYKJrSapAaiuK6sge+GmSr5LN4AlhJCLV9hP4vj F+k05Yk9tK8Zbv9gnEJPxKaSpoLyTcWyOVCwIUWGhBw8YCCnxRMJNDKBDOY29VghalBj MyvX773pB6rh6XDldd0kLXGKA059qVDLklM1uXby+f4DzUiPwDpPlGL2zYQKHFF2+zBe s4ug== X-Gm-Message-State: ANoB5pkyhXtOIuYmPQrUglbDySmNZibe8PIw2uF4sHnfO2je8O22+iXW PraZTWvSVdgRZ5xJK5PEvhX/sw== X-Google-Smtp-Source: AA0mqf5qINBTPYAP4qeg1UzaZ6wwLAd0BwvCi3JbF60z/oyrT5V6BtufJ7TAxCe0PKR19lvup9WOtA== X-Received: by 2002:a05:6a20:baa3:b0:9d:c38f:9bdd with SMTP id fb35-20020a056a20baa300b0009dc38f9bddmr20370pzb.2.1670618705014; Fri, 09 Dec 2022 12:45:05 -0800 (PST) Received: from google.com (7.104.168.34.bc.googleusercontent.com. [34.168.104.7]) by smtp.gmail.com with ESMTPSA id y10-20020aa793ca000000b0057555d35f79sm1614631pff.101.2022.12.09.12.45.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 09 Dec 2022 12:45:04 -0800 (PST) Date: Fri, 9 Dec 2022 20:45:01 +0000 From: Sean Christopherson To: Oliver Upton Cc: Marc Zyngier , James Morse , Alexandru Elisei , Paolo Bonzini , Shuah Khan , linux-arm-kernel@lists.infradead.org, kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org, kvmarm@lists.linux.dev, Ricardo Koller , linux-kselftest@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v2 4/7] KVM: selftests: Correctly initialize the VA space for TTBR0_EL1 Message-ID: References: <20221209015307.1781352-1-oliver.upton@linux.dev> <20221209015307.1781352-5-oliver.upton@linux.dev> Precedence: bulk X-Mailing-List: kvmarm@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20221209015307.1781352-5-oliver.upton@linux.dev> Message-ID: <20221209204501.ZMmpMTuuSKcD85wR4CCJgYGvimsryNfGoR-AMrxfdtc@z> On Fri, Dec 09, 2022, Oliver Upton wrote: > An interesting feature of the Arm architecture is that the stage-1 MMU > supports two distinct VA regions, controlled by TTBR{0,1}_EL1. As KVM > selftests on arm64 only uses TTBR0_EL1, the VA space is constrained to > [0, 2^(va_bits)). This is different from other architectures that > allow for addressing low and high regions of the VA space from a single > page table. > > KVM selftests' VA space allocator presumes the valid address range is > split between low and high memory based the MSB, which of course is a > poor match for arm64's TTBR0 region. > > Add a helper that correctly handles both addressing schemes with a > comment describing each. > > Signed-off-by: Oliver Upton > --- Thanks much! Looks awesome, especially the comment! Reviewed-by: Sean Christopherson > .../selftests/kvm/include/kvm_util_base.h | 1 + > tools/testing/selftests/kvm/lib/kvm_util.c | 49 ++++++++++++++++--- > 2 files changed, 44 insertions(+), 6 deletions(-) > > diff --git a/tools/testing/selftests/kvm/include/kvm_util_base.h b/tools/testing/selftests/kvm/include/kvm_util_base.h > index 6cd86da698b3..b193863d754f 100644 > --- a/tools/testing/selftests/kvm/include/kvm_util_base.h > +++ b/tools/testing/selftests/kvm/include/kvm_util_base.h > @@ -103,6 +103,7 @@ struct kvm_vm { > struct sparsebit *vpages_mapped; > bool has_irqchip; > bool pgd_created; > + bool has_split_va_space; > vm_paddr_t ucall_mmio_addr; > vm_paddr_t pgd; > vm_vaddr_t gdt; > diff --git a/tools/testing/selftests/kvm/lib/kvm_util.c b/tools/testing/selftests/kvm/lib/kvm_util.c > index a256ec67aff6..53d15f32f220 100644 > --- a/tools/testing/selftests/kvm/lib/kvm_util.c > +++ b/tools/testing/selftests/kvm/lib/kvm_util.c > @@ -186,6 +186,43 @@ const struct vm_guest_mode_params vm_guest_mode_params[] = { > _Static_assert(sizeof(vm_guest_mode_params)/sizeof(struct vm_guest_mode_params) == NUM_VM_MODES, > "Missing new mode params?"); > > +/* > + * Initializes vm->vpages_valid to match the canonical VA space of the > + * architecture. > + * > + * Most architectures split the range addressed by a single page table into a > + * low and high region based on the MSB of the VA. On architectures with this > + * behavior the VA region spans [0, 2^(va_bits - 1)), [-(2^(va_bits - 1), -1]. > + * > + * arm64 is a bit different from the rest of the crowd, as the low and high > + * regions of the VA space are addressed by distinct paging structures > + * (TTBR{0,1}_EL1). Oooh, they're different CR3s in x86 terminology? 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[34.168.104.7]) by smtp.gmail.com with ESMTPSA id y10-20020aa793ca000000b0057555d35f79sm1614631pff.101.2022.12.09.12.45.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 09 Dec 2022 12:45:04 -0800 (PST) Date: Fri, 9 Dec 2022 20:45:01 +0000 From: Sean Christopherson To: Oliver Upton Cc: Marc Zyngier , James Morse , Alexandru Elisei , Paolo Bonzini , Shuah Khan , linux-arm-kernel@lists.infradead.org, kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org, kvmarm@lists.linux.dev, Ricardo Koller , linux-kselftest@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v2 4/7] KVM: selftests: Correctly initialize the VA space for TTBR0_EL1 Message-ID: References: <20221209015307.1781352-1-oliver.upton@linux.dev> <20221209015307.1781352-5-oliver.upton@linux.dev> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20221209015307.1781352-5-oliver.upton@linux.dev> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20221209_124511_669495_D9FE0931 X-CRM114-Status: GOOD ( 21.43 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Fri, Dec 09, 2022, Oliver Upton wrote: > An interesting feature of the Arm architecture is that the stage-1 MMU > supports two distinct VA regions, controlled by TTBR{0,1}_EL1. As KVM > selftests on arm64 only uses TTBR0_EL1, the VA space is constrained to > [0, 2^(va_bits)). This is different from other architectures that > allow for addressing low and high regions of the VA space from a single > page table. > > KVM selftests' VA space allocator presumes the valid address range is > split between low and high memory based the MSB, which of course is a > poor match for arm64's TTBR0 region. > > Add a helper that correctly handles both addressing schemes with a > comment describing each. > > Signed-off-by: Oliver Upton > --- Thanks much! Looks awesome, especially the comment! Reviewed-by: Sean Christopherson > .../selftests/kvm/include/kvm_util_base.h | 1 + > tools/testing/selftests/kvm/lib/kvm_util.c | 49 ++++++++++++++++--- > 2 files changed, 44 insertions(+), 6 deletions(-) > > diff --git a/tools/testing/selftests/kvm/include/kvm_util_base.h b/tools/testing/selftests/kvm/include/kvm_util_base.h > index 6cd86da698b3..b193863d754f 100644 > --- a/tools/testing/selftests/kvm/include/kvm_util_base.h > +++ b/tools/testing/selftests/kvm/include/kvm_util_base.h > @@ -103,6 +103,7 @@ struct kvm_vm { > struct sparsebit *vpages_mapped; > bool has_irqchip; > bool pgd_created; > + bool has_split_va_space; > vm_paddr_t ucall_mmio_addr; > vm_paddr_t pgd; > vm_vaddr_t gdt; > diff --git a/tools/testing/selftests/kvm/lib/kvm_util.c b/tools/testing/selftests/kvm/lib/kvm_util.c > index a256ec67aff6..53d15f32f220 100644 > --- a/tools/testing/selftests/kvm/lib/kvm_util.c > +++ b/tools/testing/selftests/kvm/lib/kvm_util.c > @@ -186,6 +186,43 @@ const struct vm_guest_mode_params vm_guest_mode_params[] = { > _Static_assert(sizeof(vm_guest_mode_params)/sizeof(struct vm_guest_mode_params) == NUM_VM_MODES, > "Missing new mode params?"); > > +/* > + * Initializes vm->vpages_valid to match the canonical VA space of the > + * architecture. > + * > + * Most architectures split the range addressed by a single page table into a > + * low and high region based on the MSB of the VA. On architectures with this > + * behavior the VA region spans [0, 2^(va_bits - 1)), [-(2^(va_bits - 1), -1]. > + * > + * arm64 is a bit different from the rest of the crowd, as the low and high > + * regions of the VA space are addressed by distinct paging structures > + * (TTBR{0,1}_EL1). Oooh, they're different CR3s in x86 terminology? _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel