All of lore.kernel.org
 help / color / mirror / Atom feed
From: William Breathitt Gray <william.gray@linaro.org>
To: Biju Das <biju.das.jz@bp.renesas.com>
Cc: "linux-iio@vger.kernel.org" <linux-iio@vger.kernel.org>,
	Geert Uytterhoeven <geert+renesas@glider.be>,
	Chris Paterson <Chris.Paterson2@renesas.com>,
	Prabhakar Mahadev Lad <prabhakar.mahadev-lad.rj@bp.renesas.com>,
	"linux-renesas-soc@vger.kernel.org" 
	<linux-renesas-soc@vger.kernel.org>
Subject: Re: [PATCH v8 3/5] Documentation: ABI: sysfs-bus-counter: add cascade_counts_enable and external_input_phase_clock_select
Date: Sun, 11 Dec 2022 10:46:04 -0500	[thread overview]
Message-ID: <Y5X7PMSuXBcQOIhR@fedora> (raw)
In-Reply-To: <OS0PR01MB5922FFBE0E3FEE50AEF1A5B6861E9@OS0PR01MB5922.jpnprd01.prod.outlook.com>

[-- Attachment #1: Type: text/plain, Size: 2841 bytes --]

On Sun, Dec 11, 2022 at 04:12:51PM +0000, Biju Das wrote:
> Hi William Breathitt Gray,
> 
> Thanks for the feedback.
> 
> > Subject: Re: [PATCH v8 3/5] Documentation: ABI: sysfs-bus-counter: add
> > cascade_counts_enable and external_input_phase_clock_select
> > 
> > On Sat, Dec 10, 2022 at 10:21:08AM +0000, Biju Das wrote:
> > > +What:
> > 	/sys/bus/counter/devices/counterX/external_input_phase_clock_select
> > > +KernelVersion:	6.3
> > > +Contact:	linux-iio@vger.kernel.org
> > > +Description:
> > > +		This attribute selects the external clock pin for phase
> > > +		counting mode of counter X.
> > 
> > Hi Biju,
> > 
> > Remove the "This attribute" from the description, and capitalize the word
> > "counter": "Selects the external clock pin for phase counting mode of
> > Counter X."
> > 
> > > +What:
> > 	/sys/bus/counter/devices/counterX/external_input_phase_clock_select_
> > available
> > 
> > At some point in the future I should combine the *_available blocks, but
> > right now they're separated between Count and Signal configurations.
> > This external_input_phase_clock_select_available is a device-level
> > configuration so it'll need its own block as well, such as the following.
> 
> Since it is device-level configuration, I will move the below 3 blocks
> to the top of file. I hope it is ok to you.

That's okay with me, so go ahead. I think at one point I was trying to
keep the attributes listed in alphabetical order, but I haven't really
minded lately as long as the information in this file is clear.

William Breathitt Gray

> 
> +What:          /sys/bus/counter/devices/counterX/cascade_counts_enable
> +KernelVersion: 6.3
> +Contact:       linux-iio@vger.kernel.org
> +Description:
> +               Indicates the cascading of Counts on Counter X.
> +
> +               Valid attribute values are boolean.
> +
> +What:          /sys/bus/counter/devices/counterX/external_input_phase_clock_select
> +KernelVersion: 6.3
> +Contact:       linux-iio@vger.kernel.org
> +Description:
> +               Selects the external clock pin for phase counting mode of
> +               Counter X.
> +
> +               MTCLKA-MTCLKB:
> +                       MTCLKA and MTCLKB pins are selected for the external
> +                       phase clock.
> +
> +               MTCLKC-MTCLKD:
> +                       MTCLKC and MTCLKD pins are selected for the external
> +                       phase clock.
> +
> +What:          /sys/bus/counter/devices/counterX/external_input_phase_clock_select_available
> +KernelVersion:  6.3
> +Contact:        linux-iio@vger.kernel.org
> +Description:
> +                Discrete set of available values for the respective device
> +                configuration are listed in this file.
> 
> Cheers,
> Biju

[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]

  reply	other threads:[~2022-12-11 19:36 UTC|newest]

Thread overview: 11+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-12-10 10:21 [PATCH v8 0/5] Add RZ/G2L MTU3a Core, Counter and pwm driver Biju Das
2022-12-10 10:21 ` [PATCH v8 1/5] dt-bindings: timer: Document RZ/G2L MTU3a bindings Biju Das
2022-12-10 10:21 ` [PATCH v8 2/5] clocksource/drivers: Add Renesas RZ/G2L MTU3a core driver Biju Das
2022-12-10 10:21 ` [PATCH v8 3/5] Documentation: ABI: sysfs-bus-counter: add cascade_counts_enable and external_input_phase_clock_select Biju Das
2022-12-11 15:34   ` William Breathitt Gray
2022-12-11 16:12     ` Biju Das
2022-12-11 15:46       ` William Breathitt Gray [this message]
2022-12-10 10:21 ` [PATCH v8 4/5] counter: Add Renesas RZ/G2L MTU3a counter driver Biju Das
2022-12-11 16:38   ` William Breathitt Gray
2022-12-12 11:37     ` Biju Das
2022-12-10 10:21 ` [PATCH v8 5/5] pwm: Add Renesas RZ/G2L MTU3a PWM driver Biju Das

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=Y5X7PMSuXBcQOIhR@fedora \
    --to=william.gray@linaro.org \
    --cc=Chris.Paterson2@renesas.com \
    --cc=biju.das.jz@bp.renesas.com \
    --cc=geert+renesas@glider.be \
    --cc=linux-iio@vger.kernel.org \
    --cc=linux-renesas-soc@vger.kernel.org \
    --cc=prabhakar.mahadev-lad.rj@bp.renesas.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.