From: Ira Weiny <ira.weiny@intel.com>
To: Dan Williams <dan.j.williams@intel.com>
Cc: Bjorn Helgaas <bhelgaas@google.com>,
Alison Schofield <alison.schofield@intel.com>,
Vishal Verma <vishal.l.verma@intel.com>,
Davidlohr Bueso <dave@stgolabs.net>,
Jonathan Cameron <Jonathan.Cameron@huawei.com>,
Dave Jiang <dave.jiang@intel.com>, <linux-kernel@vger.kernel.org>,
<linux-pci@vger.kernel.org>, <linux-acpi@vger.kernel.org>,
<linux-cxl@vger.kernel.org>
Subject: Re: [PATCH V3 4/8] cxl/mem: Trace DRAM Event Record
Date: Sun, 11 Dec 2022 08:21:26 -0800 [thread overview]
Message-ID: <Y5YDhiDt3yeNrnGS@iweiny-mobl> (raw)
In-Reply-To: <6393b35111f0_579c12947f@dwillia2-xfh.jf.intel.com.notmuch>
On Fri, Dec 09, 2022 at 02:14:41PM -0800, Dan Williams wrote:
> ira.weiny@ wrote:
> > From: Ira Weiny <ira.weiny@intel.com>
> >
> > CXL rev 3.0 section 8.2.9.2.1.2 defines the DRAM Event Record.
> >
> > Determine if the event read is a DRAM event record and if so trace the
> > record.
> >
> > Signed-off-by: Ira Weiny <ira.weiny@intel.com>
> >
> > ---
> > Changes from v2:
> > Dan
> > Move tracing to cxl core
> > Remove trace_*_enabled() calls
> > Pass struct device to trace points
> >
> > Changes from RFC v2:
> > Output DPA flags as a separate field.
> > Ensure field names match TP_print output
> > Steven
> > prefix TRACE_EVENT with 'cxl_'
> > Jonathan
> > Formatting fix
> > Remove reserved field
> >
> > Changes from RFC:
> > Add reserved byte data
> > Use new CXL header macros
> > Jonathan
> > Use get_unaligned_le{24,16}() for unaligned fields
> > Use 'else if'
> > Dave Jiang
> > s/cxl_dram_event/dram
> > s/cxl_evt_dram_rec/cxl_event_dram
> > Adjust for new phys addr mask
> > ---
> > drivers/cxl/core/mbox.c | 13 ++++++
> > drivers/cxl/core/trace.h | 92 ++++++++++++++++++++++++++++++++++++++++
> > drivers/cxl/cxlmem.h | 23 ++++++++++
> > 3 files changed, 128 insertions(+)
> >
> > diff --git a/drivers/cxl/core/mbox.c b/drivers/cxl/core/mbox.c
> > index 0d8c66f1cdc5..2fa4645f0ed9 100644
> > --- a/drivers/cxl/core/mbox.c
> > +++ b/drivers/cxl/core/mbox.c
> > @@ -726,6 +726,14 @@ static const uuid_t gen_media_event_uuid =
> > UUID_INIT(0xfbcd0a77, 0xc260, 0x417f,
> > 0x85, 0xa9, 0x08, 0x8b, 0x16, 0x21, 0xeb, 0xa6);
> >
> > +/*
> > + * DRAM Event Record
> > + * CXL rev 3.0 section 8.2.9.2.1.2; Table 8-44
> > + */
> > +static const uuid_t dram_event_uuid =
> > + UUID_INIT(0x601dcbb3, 0x9c06, 0x4eab,
> > + 0xb8, 0xaf, 0x4e, 0x9b, 0xfb, 0x5c, 0x96, 0x24);
> > +
> > static void cxl_trace_event_record(const struct device *dev,
> > enum cxl_event_log_type type,
> > struct cxl_event_record_raw *record)
> > @@ -738,6 +746,11 @@ static void cxl_trace_event_record(const struct device *dev,
> >
> > trace_cxl_general_media(dev, type, rec);
> > return;
> > + } else if (uuid_equal(id, &dram_event_uuid)) {
> > + struct cxl_event_dram *rec = (struct cxl_event_dram *)record;
> > +
> > + trace_cxl_dram(dev, type, rec);
> > + return;
>
> I think I mentioned this before,
Sorry, I don't remember seeing that.
>
> but rather than a "return" in every
> branch just make the 'unknown' case the final else in this if block.
Sounds good. However the previous patch started this pattern so I fixed it
there and continued through these.
>
> With that feel free to add:
>
> Reviewed-by: Dan Williams <dan.j.williams@intel.com>
Thanks!
Ira
next prev parent reply other threads:[~2022-12-11 16:21 UTC|newest]
Thread overview: 25+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-12-08 5:21 [PATCH V3 0/8] CXL: Process event logs ira.weiny
2022-12-08 5:21 ` [PATCH V3 1/8] cxl/mem: Read, trace, and clear events on driver load ira.weiny
2022-12-09 17:56 ` Dan Williams
2022-12-09 21:00 ` Ira Weiny
2022-12-09 22:33 ` Dan Williams
2022-12-09 23:34 ` Ira Weiny
2022-12-12 17:58 ` Jonathan Cameron
2022-12-08 5:21 ` [PATCH V3 2/8] cxl/mem: Wire up event interrupts ira.weiny
2022-12-09 21:49 ` Dan Williams
2022-12-10 1:44 ` Ira Weiny
2022-12-08 5:21 ` [PATCH V3 3/8] cxl/mem: Trace General Media Event Record ira.weiny
2022-12-09 22:04 ` Dan Williams
2022-12-11 16:08 ` Ira Weiny
2022-12-08 5:21 ` [PATCH V3 4/8] cxl/mem: Trace DRAM " ira.weiny
2022-12-09 22:14 ` Dan Williams
2022-12-11 16:21 ` Ira Weiny [this message]
2022-12-08 5:21 ` [PATCH V3 5/8] cxl/mem: Trace Memory Module " ira.weiny
2022-12-09 22:18 ` Dan Williams
2022-12-08 5:21 ` [PATCH V3 6/8] cxl/test: Add generic mock events ira.weiny
2022-12-09 22:48 ` Dan Williams
2022-12-11 17:26 ` Ira Weiny
2022-12-08 5:21 ` [PATCH V3 7/8] cxl/test: Add specific events ira.weiny
2022-12-08 5:21 ` [PATCH V3 8/8] cxl/test: Simulate event log overflow ira.weiny
2022-12-09 22:52 ` Dan Williams
2022-12-12 4:21 ` Ira Weiny
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