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From: William Breathitt Gray <william.gray@linaro.org>
To: Biju Das <biju.das.jz@bp.renesas.com>
Cc: linux-iio@vger.kernel.org,
	Geert Uytterhoeven <geert+renesas@glider.be>,
	Chris Paterson <chris.paterson2@renesas.com>,
	Prabhakar Mahadev Lad <prabhakar.mahadev-lad.rj@bp.renesas.com>,
	linux-renesas-soc@vger.kernel.org
Subject: Re: [PATCH v10 4/5] counter: Add Renesas RZ/G2L MTU3a counter driver
Date: Fri, 16 Dec 2022 16:45:19 -0500	[thread overview]
Message-ID: <Y5zm78UPXQMc3gjp@fedora> (raw)
In-Reply-To: <20221216205028.340795-5-biju.das.jz@bp.renesas.com>

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On Fri, Dec 16, 2022 at 08:50:27PM +0000, Biju Das wrote:
> Add RZ/G2L MTU3a counter driver. This IP supports the following
> phase counting modes on MTU1 and MTU2 channels
> 
> 1) 16-bit phase counting modes on MTU1 and MTU2 channels.
> 2) 32-bit phase counting mode by cascading MTU1 and MTU2 channels.
> 
> This patch adds 3 counter value channels.
> 	count0: 16-bit phase counter value channel on MTU1
> 	count1: 16-bit phase counter value channel on MTU2
> 	count2: 32-bit phase counter value channel by cascading
>                 MTU1 and MTU2 channels.
> 
> The external input phase clock pin for the counter value channels
> are as follows:
> 	count0: "MTCLKA-MTCLKB"
> 	count1: "MTCLKA-MTCLKB" or "MTCLKC-MTCLKD"
> 	count2: "MTCLKA-MTCLKB" or "MTCLKC-MTCLKD"
> 
> Use the sysfs variable "external_input_phase_clock_select" to select the
> external input phase clock pin and "cascade_counts_enable" to enable/
> disable cascading of channels.
> 
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>

Hi Biju,

You're missing an entry for this driver in the MAINTAINERS file so
please add one. The code for this version looks good so you're welcome
to add my Rb line.

Reviewed-by: William Breathitt Gray <william.gray@linaro.org>

I do have a minor suggestion below.

> +static struct counter_count rz_mtu3_counts[] = {
> +	{
> +		.id = RZ_MTU3_16_BIT_MTU1_CH,
> +		.name = "Channel 1 Count",
> +		.functions_list = rz_mtu3_count_functions,
> +		.num_functions = ARRAY_SIZE(rz_mtu3_count_functions),
> +		.synapses = rz_mtu3_mtu1_count_synapses,
> +		.num_synapses = ARRAY_SIZE(rz_mtu3_mtu1_count_synapses),
> +		.ext = rz_mtu3_count_ext,
> +		.num_ext = ARRAY_SIZE(rz_mtu3_count_ext),
> +	},
> +	{
> +		.id = RZ_MTU3_16_BIT_MTU2_CH,
> +		.name = "Channel 2 Count",
> +		.functions_list = rz_mtu3_count_functions,
> +		.num_functions = ARRAY_SIZE(rz_mtu3_count_functions),
> +		.synapses = rz_mtu3_mtu2_count_synapses,
> +		.num_synapses = ARRAY_SIZE(rz_mtu3_mtu2_count_synapses),
> +		.ext = rz_mtu3_count_ext,
> +		.num_ext = ARRAY_SIZE(rz_mtu3_count_ext),
> +	},
> +	{
> +		.id = RZ_MTU3_32_BIT_CH,
> +		.name = "Channel 1 and 2 (combined) Count",

These channels are actually cascaded, so replacing "combined" with
"cascaded" here would be better.

William Breathitt Gray

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  reply	other threads:[~2022-12-16 21:47 UTC|newest]

Thread overview: 13+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-12-16 20:50 [PATCH v10 0/5] Add RZ/G2L MTU3a Core, Counter and pwm driver Biju Das
2022-12-16 20:50 ` [PATCH v10 1/5] dt-bindings: timer: Document RZ/G2L MTU3a bindings Biju Das
2022-12-16 20:50 ` [PATCH v10 2/5] clocksource/drivers: Add Renesas RZ/G2L MTU3a core driver Biju Das
2023-01-09  9:57   ` Biju Das
2022-12-16 20:50 ` [PATCH v10 3/5] Documentation: ABI: sysfs-bus-counter: add cascade_counts_enable and external_input_phase_clock_select Biju Das
2022-12-16 20:50 ` [PATCH v10 4/5] counter: Add Renesas RZ/G2L MTU3a counter driver Biju Das
2022-12-16 21:45   ` William Breathitt Gray [this message]
2023-01-09  9:06     ` Biju Das
2022-12-19  8:40   ` Geert Uytterhoeven
2023-01-09 14:28     ` Biju Das
2023-01-09 14:38       ` Biju Das
2022-12-16 20:50 ` [PATCH v10 5/5] pwm: Add Renesas RZ/G2L MTU3a PWM driver Biju Das
2023-01-09  9:53   ` Biju Das

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