From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mm01.cs.columbia.edu (mm01.cs.columbia.edu [128.59.11.253]) by smtp.lore.kernel.org (Postfix) with ESMTP id EF72FC4167B for ; Wed, 21 Dec 2022 16:50:41 +0000 (UTC) Received: from localhost (localhost [127.0.0.1]) by mm01.cs.columbia.edu (Postfix) with ESMTP id 851FF4B881; Wed, 21 Dec 2022 11:50:41 -0500 (EST) X-Virus-Scanned: at lists.cs.columbia.edu Authentication-Results: mm01.cs.columbia.edu (amavisd-new); dkim=softfail (fail, message has been altered) header.i=@linux.dev Received: from mm01.cs.columbia.edu ([127.0.0.1]) by localhost (mm01.cs.columbia.edu [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id xnWkn29X6CtU; Wed, 21 Dec 2022 11:50:39 -0500 (EST) Received: from mm01.cs.columbia.edu (localhost [127.0.0.1]) by mm01.cs.columbia.edu (Postfix) with ESMTP id 6311B4B880; Wed, 21 Dec 2022 11:50:39 -0500 (EST) Received: from localhost (localhost [127.0.0.1]) by mm01.cs.columbia.edu (Postfix) with ESMTP id 1D7564B87B for ; Wed, 21 Dec 2022 11:50:38 -0500 (EST) X-Virus-Scanned: at lists.cs.columbia.edu Received: from mm01.cs.columbia.edu ([127.0.0.1]) by localhost (mm01.cs.columbia.edu [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id ZmwDbBr9XrF8 for ; Wed, 21 Dec 2022 11:50:36 -0500 (EST) Received: from out2.migadu.com (out2.migadu.com [188.165.223.204]) by mm01.cs.columbia.edu (Postfix) with ESMTPS id 98A0F4B86C for ; Wed, 21 Dec 2022 11:50:36 -0500 (EST) Date: Wed, 21 Dec 2022 16:50:30 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.dev; s=key1; t=1671641435; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: in-reply-to:in-reply-to:references:references; bh=Xdjf8bxiYHpI/EXjIs05wPVvAMrqG6J7dZ0Cm96qYYk=; b=qxoDmMVkSPwg3Qz24+AUYA0y6lpWSkYf2PUOZNWsPkHLlkZmsiNsyWI3G8/uHbGwAMUeUA JQf9aZ5PKPis0vEWtlTS1mvtDL3/dB8Hvl3yvja4684hiQ4Ws8MJp3lzApIvYoozbbHiux QIczvU9G9oZOR1c6d/2ickYaol8Yw5A= X-Report-Abuse: Please report any abuse attempt to abuse@migadu.com and include these headers. From: Oliver Upton To: Marc Zyngier Subject: Re: [PATCH 1/3] KVM: arm64: Fix S1PTW handling on RO memslots Message-ID: References: <20221220200923.1532710-1-maz@kernel.org> <20221220200923.1532710-2-maz@kernel.org> <86pmcdaylx.wl-maz@kernel.org> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <86pmcdaylx.wl-maz@kernel.org> X-Migadu-Flow: FLOW_OUT Cc: kvm@vger.kernel.org, Will Deacon , stable@vger.kernel.org, kvmarm@lists.linux.dev, kvmarm@lists.cs.columbia.edu, linux-arm-kernel@lists.infradead.org X-BeenThere: kvmarm@lists.cs.columbia.edu X-Mailman-Version: 2.1.14 Precedence: list List-Id: Where KVM/ARM decisions are made List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Errors-To: kvmarm-bounces@lists.cs.columbia.edu Sender: kvmarm-bounces@lists.cs.columbia.edu On Wed, Dec 21, 2022 at 09:35:06AM +0000, Marc Zyngier wrote: [...] > > > + if (kvm_vcpu_abt_iss1tw(vcpu)) { > > > + /* > > > + * Only a permission fault on a S1PTW should be > > > + * considered as a write. Otherwise, page tables baked > > > + * in a read-only memslot will result in an exception > > > + * being delivered in the guest. > > > > Somewhat of a tangent, but: > > > > Aren't we somewhat unaligned with the KVM UAPI by injecting an > > exception in this case? I know we've been doing it for a while, but it > > flies in the face of the rules outlined in the > > KVM_SET_USER_MEMORY_REGION documentation. > > That's an interesting point, and I certainly haven't considered that > for faults introduced by page table walks. > > I'm not sure what userspace can do with that though. The problem is > that this is a write for which we don't have useful data: although we > know it is a page-table walker access, we don't know what it was about > to write. The instruction that caused the write is meaningless (it > could either be a load, a store, or an instruction fetch). How do you > populate the data[] field then? > > If anything, this is closer to KVM_EXIT_ARM_NISV, for which we give > userspace the full ESR and ask it to sort it out. I doubt it will be > able to, but hey, maybe it is worth a shot. This would need to be a > different exit reason though, as NISV is explicitly for non-memslot > stuff. > > In any case, the documentation for KVM_SET_USER_MEMORY_REGION needs to > reflect the fact that KVM_EXIT_MMIO cannot represent a fault due to a > S1 PTW. Oh I completely agree with you here. I probably should have said before, I think the exit would be useless anyway. Getting the documentation in line with the intended behavior seems to be the best fix. > > > > > + * The drawback is that we end-up fauling twice if the > > > > typo: s/fauling/faulting/ > > > > > + * guest is using any of HW AF/DB: a translation fault > > > + * to map the page containing the PT (read only at > > > + * first), then a permission fault to allow the flags > > > + * to be set. > > > + */ > > > + switch (kvm_vcpu_trap_get_fault_type(vcpu)) { > > > + case ESR_ELx_FSC_PERM: > > > + return true; > > > + default: > > > + return false; > > > + } > > > + } > > > > > > if (kvm_vcpu_trap_is_iabt(vcpu)) > > > return false; > > > -- > > > 2.34.1 > > > > > > > Besides the changelog/comment suggestions, the patch looks good to me. > > > > Reviewed-by: Oliver Upton > > Thanks for the quick review! I'll wait a bit before respinning the > series, as I'd like to get closure on the UAPI point you have raised. I'm satisfied if you are :) -- Thanks, Oliver _______________________________________________ kvmarm mailing list kvmarm@lists.cs.columbia.edu https://lists.cs.columbia.edu/mailman/listinfo/kvmarm From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from out2.migadu.com (out2.migadu.com [188.165.223.204]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 53E0828FC for ; Wed, 21 Dec 2022 16:50:37 +0000 (UTC) Date: Wed, 21 Dec 2022 16:50:30 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.dev; s=key1; t=1671641435; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: in-reply-to:in-reply-to:references:references; bh=Xdjf8bxiYHpI/EXjIs05wPVvAMrqG6J7dZ0Cm96qYYk=; b=qxoDmMVkSPwg3Qz24+AUYA0y6lpWSkYf2PUOZNWsPkHLlkZmsiNsyWI3G8/uHbGwAMUeUA JQf9aZ5PKPis0vEWtlTS1mvtDL3/dB8Hvl3yvja4684hiQ4Ws8MJp3lzApIvYoozbbHiux QIczvU9G9oZOR1c6d/2ickYaol8Yw5A= X-Report-Abuse: Please report any abuse attempt to abuse@migadu.com and include these headers. From: Oliver Upton To: Marc Zyngier Cc: kvmarm@lists.cs.columbia.edu, kvmarm@lists.linux.dev, kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, James Morse , Suzuki K Poulose , Alexandru Elisei , Ard Biesheuvel , Will Deacon , Quentin Perret , stable@vger.kernel.org Subject: Re: [PATCH 1/3] KVM: arm64: Fix S1PTW handling on RO memslots Message-ID: References: <20221220200923.1532710-1-maz@kernel.org> <20221220200923.1532710-2-maz@kernel.org> <86pmcdaylx.wl-maz@kernel.org> Precedence: bulk X-Mailing-List: kvmarm@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <86pmcdaylx.wl-maz@kernel.org> X-Migadu-Flow: FLOW_OUT Message-ID: <20221221165030.ogDX6j1vGJAgDSQQFvSVpJJr6Ika41kFpmNkoIMlNm8@z> On Wed, Dec 21, 2022 at 09:35:06AM +0000, Marc Zyngier wrote: [...] > > > + if (kvm_vcpu_abt_iss1tw(vcpu)) { > > > + /* > > > + * Only a permission fault on a S1PTW should be > > > + * considered as a write. Otherwise, page tables baked > > > + * in a read-only memslot will result in an exception > > > + * being delivered in the guest. > > > > Somewhat of a tangent, but: > > > > Aren't we somewhat unaligned with the KVM UAPI by injecting an > > exception in this case? I know we've been doing it for a while, but it > > flies in the face of the rules outlined in the > > KVM_SET_USER_MEMORY_REGION documentation. > > That's an interesting point, and I certainly haven't considered that > for faults introduced by page table walks. > > I'm not sure what userspace can do with that though. The problem is > that this is a write for which we don't have useful data: although we > know it is a page-table walker access, we don't know what it was about > to write. The instruction that caused the write is meaningless (it > could either be a load, a store, or an instruction fetch). How do you > populate the data[] field then? > > If anything, this is closer to KVM_EXIT_ARM_NISV, for which we give > userspace the full ESR and ask it to sort it out. I doubt it will be > able to, but hey, maybe it is worth a shot. This would need to be a > different exit reason though, as NISV is explicitly for non-memslot > stuff. > > In any case, the documentation for KVM_SET_USER_MEMORY_REGION needs to > reflect the fact that KVM_EXIT_MMIO cannot represent a fault due to a > S1 PTW. Oh I completely agree with you here. I probably should have said before, I think the exit would be useless anyway. Getting the documentation in line with the intended behavior seems to be the best fix. > > > > > + * The drawback is that we end-up fauling twice if the > > > > typo: s/fauling/faulting/ > > > > > + * guest is using any of HW AF/DB: a translation fault > > > + * to map the page containing the PT (read only at > > > + * first), then a permission fault to allow the flags > > > + * to be set. > > > + */ > > > + switch (kvm_vcpu_trap_get_fault_type(vcpu)) { > > > + case ESR_ELx_FSC_PERM: > > > + return true; > > > + default: > > > + return false; > > > + } > > > + } > > > > > > if (kvm_vcpu_trap_is_iabt(vcpu)) > > > return false; > > > -- > > > 2.34.1 > > > > > > > Besides the changelog/comment suggestions, the patch looks good to me. > > > > Reviewed-by: Oliver Upton > > Thanks for the quick review! I'll wait a bit before respinning the > series, as I'd like to get closure on the UAPI point you have raised. I'm satisfied if you are :) -- Thanks, Oliver From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id AEDDBC4332F for ; Wed, 21 Dec 2022 16:51:58 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:Cc:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=bqiWR9upQi1vKLxz4+xVU4eVamWDTBGdt8sOfKhwLPQ=; b=aShjECdnnOax6+ IU0lriUkAKlJsEtb3nROm0/DNXc5eNZ5NgN7RDEPdIg6+lc8AU2JO3UkGbHe+uknNSnrQChDqFcbJ sJKQcQosRcmBTphzAwczxY4SLPQSd/jpK5G12RczLfn7u883hfBp1/axINHOkqF9r+VPAUIvY3yld 0aJEFpWUgEpjj2+AXOzNt7eatjf0eDfK11MHy3tostKJxpkrDa9IhgShzeFD818gBJYEfIdQ6LBQJ VFDbKvNltPWfOh113f9QEhkTbF5ki5keOd724hJcDzoLHJDOYvJJAY9QKNr86+YXuKweUdWVvPLax U+5q8TZZCz8TWovSHakg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1p82Iz-00HAxO-1s; Wed, 21 Dec 2022 16:50:57 +0000 Received: from out2.migadu.com ([2001:41d0:2:aacc::]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1p82Ih-00HApY-AL for linux-arm-kernel@lists.infradead.org; Wed, 21 Dec 2022 16:50:42 +0000 Date: Wed, 21 Dec 2022 16:50:30 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.dev; s=key1; t=1671641435; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: in-reply-to:in-reply-to:references:references; bh=Xdjf8bxiYHpI/EXjIs05wPVvAMrqG6J7dZ0Cm96qYYk=; b=qxoDmMVkSPwg3Qz24+AUYA0y6lpWSkYf2PUOZNWsPkHLlkZmsiNsyWI3G8/uHbGwAMUeUA JQf9aZ5PKPis0vEWtlTS1mvtDL3/dB8Hvl3yvja4684hiQ4Ws8MJp3lzApIvYoozbbHiux QIczvU9G9oZOR1c6d/2ickYaol8Yw5A= X-Report-Abuse: Please report any abuse attempt to abuse@migadu.com and include these headers. From: Oliver Upton To: Marc Zyngier Cc: kvmarm@lists.cs.columbia.edu, kvmarm@lists.linux.dev, kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, James Morse , Suzuki K Poulose , Alexandru Elisei , Ard Biesheuvel , Will Deacon , Quentin Perret , stable@vger.kernel.org Subject: Re: [PATCH 1/3] KVM: arm64: Fix S1PTW handling on RO memslots Message-ID: References: <20221220200923.1532710-1-maz@kernel.org> <20221220200923.1532710-2-maz@kernel.org> <86pmcdaylx.wl-maz@kernel.org> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <86pmcdaylx.wl-maz@kernel.org> X-Migadu-Flow: FLOW_OUT X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20221221_085040_401905_1691D8E5 X-CRM114-Status: GOOD ( 31.47 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Wed, Dec 21, 2022 at 09:35:06AM +0000, Marc Zyngier wrote: [...] > > > + if (kvm_vcpu_abt_iss1tw(vcpu)) { > > > + /* > > > + * Only a permission fault on a S1PTW should be > > > + * considered as a write. Otherwise, page tables baked > > > + * in a read-only memslot will result in an exception > > > + * being delivered in the guest. > > > > Somewhat of a tangent, but: > > > > Aren't we somewhat unaligned with the KVM UAPI by injecting an > > exception in this case? I know we've been doing it for a while, but it > > flies in the face of the rules outlined in the > > KVM_SET_USER_MEMORY_REGION documentation. > > That's an interesting point, and I certainly haven't considered that > for faults introduced by page table walks. > > I'm not sure what userspace can do with that though. The problem is > that this is a write for which we don't have useful data: although we > know it is a page-table walker access, we don't know what it was about > to write. The instruction that caused the write is meaningless (it > could either be a load, a store, or an instruction fetch). How do you > populate the data[] field then? > > If anything, this is closer to KVM_EXIT_ARM_NISV, for which we give > userspace the full ESR and ask it to sort it out. I doubt it will be > able to, but hey, maybe it is worth a shot. This would need to be a > different exit reason though, as NISV is explicitly for non-memslot > stuff. > > In any case, the documentation for KVM_SET_USER_MEMORY_REGION needs to > reflect the fact that KVM_EXIT_MMIO cannot represent a fault due to a > S1 PTW. Oh I completely agree with you here. I probably should have said before, I think the exit would be useless anyway. Getting the documentation in line with the intended behavior seems to be the best fix. > > > > > + * The drawback is that we end-up fauling twice if the > > > > typo: s/fauling/faulting/ > > > > > + * guest is using any of HW AF/DB: a translation fault > > > + * to map the page containing the PT (read only at > > > + * first), then a permission fault to allow the flags > > > + * to be set. > > > + */ > > > + switch (kvm_vcpu_trap_get_fault_type(vcpu)) { > > > + case ESR_ELx_FSC_PERM: > > > + return true; > > > + default: > > > + return false; > > > + } > > > + } > > > > > > if (kvm_vcpu_trap_is_iabt(vcpu)) > > > return false; > > > -- > > > 2.34.1 > > > > > > > Besides the changelog/comment suggestions, the patch looks good to me. > > > > Reviewed-by: Oliver Upton > > Thanks for the quick review! I'll wait a bit before respinning the > series, as I'd like to get closure on the UAPI point you have raised. I'm satisfied if you are :) -- Thanks, Oliver _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel