From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6FB61C4708E for ; Thu, 5 Jan 2023 18:15:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234263AbjAESPK (ORCPT ); Thu, 5 Jan 2023 13:15:10 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46096 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232101AbjAESPI (ORCPT ); Thu, 5 Jan 2023 13:15:08 -0500 Received: from dfw.source.kernel.org (dfw.source.kernel.org [139.178.84.217]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9DE2F4FCCF; Thu, 5 Jan 2023 10:15:07 -0800 (PST) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 3498761BEC; Thu, 5 Jan 2023 18:15:07 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 52EDBC433D2; Thu, 5 Jan 2023 18:15:01 +0000 (UTC) Date: Thu, 5 Jan 2023 18:14:58 +0000 From: Catalin Marinas To: Yicong Yang Cc: akpm@linux-foundation.org, linux-mm@kvack.org, linux-arm-kernel@lists.infradead.org, x86@kernel.org, will@kernel.org, anshuman.khandual@arm.com, linux-doc@vger.kernel.org, corbet@lwn.net, peterz@infradead.org, arnd@arndb.de, punit.agrawal@bytedance.com, linux-kernel@vger.kernel.org, darren@os.amperecomputing.com, yangyicong@hisilicon.com, huzhanyuan@oppo.com, lipeifeng@oppo.com, zhangshiming@oppo.com, guojian@oppo.com, realmz6@gmail.com, linux-mips@vger.kernel.org, openrisc@lists.librecores.org, linuxppc-dev@lists.ozlabs.org, linux-riscv@lists.infradead.org, linux-s390@vger.kernel.org, Barry Song <21cnbao@gmail.com>, wangkefeng.wang@huawei.com, xhao@linux.alibaba.com, prime.zeng@hisilicon.com, Barry Song , Nadav Amit , Mel Gorman Subject: Re: [PATCH v7 2/2] arm64: support batched/deferred tlb shootdown during page reclamation Message-ID: References: <20221117082648.47526-1-yangyicong@huawei.com> <20221117082648.47526-3-yangyicong@huawei.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20221117082648.47526-3-yangyicong@huawei.com> Precedence: bulk List-ID: X-Mailing-List: linux-doc@vger.kernel.org On Thu, Nov 17, 2022 at 04:26:48PM +0800, Yicong Yang wrote: > It is tested on 4,8,128 CPU platforms and shows to be beneficial on > large systems but may not have improvement on small systems like on > a 4 CPU platform. So make ARCH_WANT_BATCHED_UNMAP_TLB_FLUSH depends > on CONFIG_EXPERT for this stage and make this disabled on systems > with less than 8 CPUs. User can modify this threshold according to > their own platforms by CONFIG_NR_CPUS_FOR_BATCHED_TLB. What's the overhead of such batching on systems with 4 or fewer CPUs? If it isn't noticeable, I'd rather have it always on than some number chosen on whichever SoC you tested. Another option would be to make this a sysctl tunable. > .../features/vm/TLB/arch-support.txt | 2 +- > arch/arm64/Kconfig | 6 +++ > arch/arm64/include/asm/tlbbatch.h | 12 +++++ > arch/arm64/include/asm/tlbflush.h | 52 ++++++++++++++++++- > arch/x86/include/asm/tlbflush.h | 5 +- > include/linux/mm_types_task.h | 4 +- > mm/rmap.c | 10 ++-- Please keep any function prototype changes in a preparatory patch so that the arm64 one only introduces the arch specific changes. Easier to review. > +static inline bool arch_tlbbatch_should_defer(struct mm_struct *mm) > +{ > + /* > + * TLB batched flush is proved to be beneficial for systems with large > + * number of CPUs, especially system with more than 8 CPUs. TLB shutdown > + * is cheap on small systems which may not need this feature. So use > + * a threshold for enabling this to avoid potential side effects on > + * these platforms. > + */ > + if (num_online_cpus() < CONFIG_ARM64_NR_CPUS_FOR_BATCHED_TLB) > + return false; The x86 implementation tracks the cpumask of where a task has run. We don't have such tracking on arm64 and I don't think it matters. As noticed/described in this series, the bottleneck is the actual DSB synchronisation (which sends a DVM Sync message to all the other CPUs and waits for a DVM Complete response). So I think it makes sense not to bother with an mm_cpumask(). What this patch aims to optimise is actually the number of DSBs issued on an SMP system by ptep_clear_flush(). The DVM is not an architected concept (well, it's part of AMBA AXI). I'd be curious to know how such patch behaves on Apple's M1/M2 hardware. My preference would be to have this always on for num_online_cpus() > 1 if there's no overhead. -- Catalin From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 0404AC3DA7D for ; Thu, 5 Jan 2023 21:03:33 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:Cc:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=txMpkHb1dBQzN2FuqqQXHQ/z1M/sC/6t8fOPDpgKSWg=; b=1cMRjsDAhrfvxG S8Z+6M2SzHAIwBLlz9/mUxS6uHN4YQ73y04T/4rMy6uzl3r3IX+gGVVkokPxo6f5sz3q15Gk5UubW fG/nc6v8SGb21j/TXbytS2FQOznlptguctmroddRK0hKu8B2naUmTbxQ5iabUgvN3dLUKuXv7iuxA Jgujxr6QUS5UNMGaGc7gD8A7FgtS7cRTCGLjoDO3pmfViym1CKT3NldyXxo1DIurM0FmyZ6DUtHum Xr2iMU3BJJSstVsplHPaVOjzchSDrBC7idkcuXXJWf1Ao+4O1Mi3IkTblrctJdGjERTLHr+nJgvXG ISyBkvidGM+UtS1p0Xow==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1pDXOU-00EsVy-6u; Thu, 05 Jan 2023 21:03:22 +0000 Received: from dfw.source.kernel.org ([139.178.84.217]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1pDUlh-00DRLh-1h; Thu, 05 Jan 2023 18:15:10 +0000 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 292AE61BD1; Thu, 5 Jan 2023 18:15:07 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 52EDBC433D2; Thu, 5 Jan 2023 18:15:01 +0000 (UTC) Date: Thu, 5 Jan 2023 18:14:58 +0000 From: Catalin Marinas To: Yicong Yang Cc: akpm@linux-foundation.org, linux-mm@kvack.org, linux-arm-kernel@lists.infradead.org, x86@kernel.org, will@kernel.org, anshuman.khandual@arm.com, linux-doc@vger.kernel.org, corbet@lwn.net, peterz@infradead.org, arnd@arndb.de, punit.agrawal@bytedance.com, linux-kernel@vger.kernel.org, darren@os.amperecomputing.com, yangyicong@hisilicon.com, huzhanyuan@oppo.com, lipeifeng@oppo.com, zhangshiming@oppo.com, guojian@oppo.com, realmz6@gmail.com, linux-mips@vger.kernel.org, openrisc@lists.librecores.org, linuxppc-dev@lists.ozlabs.org, linux-riscv@lists.infradead.org, linux-s390@vger.kernel.org, Barry Song <21cnbao@gmail.com>, wangkefeng.wang@huawei.com, xhao@linux.alibaba.com, prime.zeng@hisilicon.com, Barry Song , Nadav Amit , Mel Gorman Subject: Re: [PATCH v7 2/2] arm64: support batched/deferred tlb shootdown during page reclamation Message-ID: References: <20221117082648.47526-1-yangyicong@huawei.com> <20221117082648.47526-3-yangyicong@huawei.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20221117082648.47526-3-yangyicong@huawei.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230105_101509_204010_A9B48938 X-CRM114-Status: GOOD ( 23.87 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org On Thu, Nov 17, 2022 at 04:26:48PM +0800, Yicong Yang wrote: > It is tested on 4,8,128 CPU platforms and shows to be beneficial on > large systems but may not have improvement on small systems like on > a 4 CPU platform. So make ARCH_WANT_BATCHED_UNMAP_TLB_FLUSH depends > on CONFIG_EXPERT for this stage and make this disabled on systems > with less than 8 CPUs. User can modify this threshold according to > their own platforms by CONFIG_NR_CPUS_FOR_BATCHED_TLB. What's the overhead of such batching on systems with 4 or fewer CPUs? If it isn't noticeable, I'd rather have it always on than some number chosen on whichever SoC you tested. Another option would be to make this a sysctl tunable. > .../features/vm/TLB/arch-support.txt | 2 +- > arch/arm64/Kconfig | 6 +++ > arch/arm64/include/asm/tlbbatch.h | 12 +++++ > arch/arm64/include/asm/tlbflush.h | 52 ++++++++++++++++++- > arch/x86/include/asm/tlbflush.h | 5 +- > include/linux/mm_types_task.h | 4 +- > mm/rmap.c | 10 ++-- Please keep any function prototype changes in a preparatory patch so that the arm64 one only introduces the arch specific changes. Easier to review. > +static inline bool arch_tlbbatch_should_defer(struct mm_struct *mm) > +{ > + /* > + * TLB batched flush is proved to be beneficial for systems with large > + * number of CPUs, especially system with more than 8 CPUs. TLB shutdown > + * is cheap on small systems which may not need this feature. So use > + * a threshold for enabling this to avoid potential side effects on > + * these platforms. > + */ > + if (num_online_cpus() < CONFIG_ARM64_NR_CPUS_FOR_BATCHED_TLB) > + return false; The x86 implementation tracks the cpumask of where a task has run. We don't have such tracking on arm64 and I don't think it matters. As noticed/described in this series, the bottleneck is the actual DSB synchronisation (which sends a DVM Sync message to all the other CPUs and waits for a DVM Complete response). So I think it makes sense not to bother with an mm_cpumask(). What this patch aims to optimise is actually the number of DSBs issued on an SMP system by ptep_clear_flush(). The DVM is not an architected concept (well, it's part of AMBA AXI). I'd be curious to know how such patch behaves on Apple's M1/M2 hardware. My preference would be to have this always on for num_online_cpus() > 1 if there's no overhead. -- Catalin _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.librecores.org (lists.librecores.org [88.198.125.70]) by smtp.lore.kernel.org (Postfix) with ESMTP id 102A1C54EBD for ; Thu, 5 Jan 2023 18:15:11 +0000 (UTC) Received: from [172.31.1.100] (localhost.localdomain [127.0.0.1]) by mail.librecores.org (Postfix) with ESMTP id 886CE24C4B; Thu, 5 Jan 2023 19:15:10 +0100 (CET) Received: from dfw.source.kernel.org (dfw.source.kernel.org [139.178.84.217]) by mail.librecores.org (Postfix) with ESMTPS id 61D3224C5C for ; Thu, 5 Jan 2023 19:15:08 +0100 (CET) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 292AE61BD1; Thu, 5 Jan 2023 18:15:07 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 52EDBC433D2; Thu, 5 Jan 2023 18:15:01 +0000 (UTC) Date: Thu, 5 Jan 2023 18:14:58 +0000 From: Catalin Marinas To: Yicong Yang Subject: Re: [PATCH v7 2/2] arm64: support batched/deferred tlb shootdown during page reclamation Message-ID: References: <20221117082648.47526-1-yangyicong@huawei.com> <20221117082648.47526-3-yangyicong@huawei.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20221117082648.47526-3-yangyicong@huawei.com> X-BeenThere: openrisc@lists.librecores.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: Discussion around the OpenRISC processor List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: wangkefeng.wang@huawei.com, prime.zeng@hisilicon.com, realmz6@gmail.com, linux-doc@vger.kernel.org, peterz@infradead.org, linux-kernel@vger.kernel.org, linux-mm@kvack.org, Nadav Amit , punit.agrawal@bytedance.com, linux-riscv@lists.infradead.org, will@kernel.org, linux-s390@vger.kernel.org, zhangshiming@oppo.com, lipeifeng@oppo.com, corbet@lwn.net, x86@kernel.org, Barry Song <21cnbao@gmail.com>, Mel Gorman , arnd@arndb.de, anshuman.khandual@arm.com, Barry Song , openrisc@lists.librecores.org, darren@os.amperecomputing.com, yangyicong@hisilicon.com, linux-arm-kernel@lists.infradead.org, guojian@oppo.com, xhao@linux.alibaba.com, linux-mips@vger.kernel.org, huzhanyuan@oppo.com, akpm@linux-foundation.org, linuxppc-dev@lists.ozlabs.org Errors-To: openrisc-bounces@lists.librecores.org Sender: "OpenRISC" On Thu, Nov 17, 2022 at 04:26:48PM +0800, Yicong Yang wrote: > It is tested on 4,8,128 CPU platforms and shows to be beneficial on > large systems but may not have improvement on small systems like on > a 4 CPU platform. So make ARCH_WANT_BATCHED_UNMAP_TLB_FLUSH depends > on CONFIG_EXPERT for this stage and make this disabled on systems > with less than 8 CPUs. User can modify this threshold according to > their own platforms by CONFIG_NR_CPUS_FOR_BATCHED_TLB. What's the overhead of such batching on systems with 4 or fewer CPUs? If it isn't noticeable, I'd rather have it always on than some number chosen on whichever SoC you tested. Another option would be to make this a sysctl tunable. > .../features/vm/TLB/arch-support.txt | 2 +- > arch/arm64/Kconfig | 6 +++ > arch/arm64/include/asm/tlbbatch.h | 12 +++++ > arch/arm64/include/asm/tlbflush.h | 52 ++++++++++++++++++- > arch/x86/include/asm/tlbflush.h | 5 +- > include/linux/mm_types_task.h | 4 +- > mm/rmap.c | 10 ++-- Please keep any function prototype changes in a preparatory patch so that the arm64 one only introduces the arch specific changes. Easier to review. > +static inline bool arch_tlbbatch_should_defer(struct mm_struct *mm) > +{ > + /* > + * TLB batched flush is proved to be beneficial for systems with large > + * number of CPUs, especially system with more than 8 CPUs. TLB shutdown > + * is cheap on small systems which may not need this feature. So use > + * a threshold for enabling this to avoid potential side effects on > + * these platforms. > + */ > + if (num_online_cpus() < CONFIG_ARM64_NR_CPUS_FOR_BATCHED_TLB) > + return false; The x86 implementation tracks the cpumask of where a task has run. We don't have such tracking on arm64 and I don't think it matters. As noticed/described in this series, the bottleneck is the actual DSB synchronisation (which sends a DVM Sync message to all the other CPUs and waits for a DVM Complete response). So I think it makes sense not to bother with an mm_cpumask(). What this patch aims to optimise is actually the number of DSBs issued on an SMP system by ptep_clear_flush(). The DVM is not an architected concept (well, it's part of AMBA AXI). I'd be curious to know how such patch behaves on Apple's M1/M2 hardware. My preference would be to have this always on for num_online_cpus() > 1 if there's no overhead. -- Catalin From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id ACBE5C3DA7D for ; Thu, 5 Jan 2023 21:03:22 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:Cc:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=shSLYialsDR48DKRzLJ47bS0bid4r00pPLN8oDP4RB4=; b=SJWVB5pDeqKF/8 WVphkyu7/Z8ACHphjmezUw2bf2chW9/HQrGJSdGeCdBuha45FiA+lA/hkx4VYdGS8E5lU+mNXFgcx kMOU0m2XARSrcviAO3LXogNt9pwPbIAETdzZvWRiuF9+affydLPh+J4/Qbo/2eSHZgd/qn02zJtCE Q/okM+Z4eQ9iUgSkEn45ULWVK4sbz5J7PaOMuTgFwQyHaPhr4XWC7DAJXwNg3Sqlccms44QY5Avrf yp7QOQrvnnunuxnEYCzvF2GP0efiIgad71cUU69oqKuHvXhDkIQLdfLL/wmJ1gVAswZKtgBDXNP+5 8RvYe5QDCRxnCpAg0HzA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1pDXNe-00EryM-48; Thu, 05 Jan 2023 21:02:30 +0000 Received: from dfw.source.kernel.org ([139.178.84.217]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1pDUlh-00DRLh-1h; Thu, 05 Jan 2023 18:15:10 +0000 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 292AE61BD1; Thu, 5 Jan 2023 18:15:07 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 52EDBC433D2; Thu, 5 Jan 2023 18:15:01 +0000 (UTC) Date: Thu, 5 Jan 2023 18:14:58 +0000 From: Catalin Marinas To: Yicong Yang Cc: akpm@linux-foundation.org, linux-mm@kvack.org, linux-arm-kernel@lists.infradead.org, x86@kernel.org, will@kernel.org, anshuman.khandual@arm.com, linux-doc@vger.kernel.org, corbet@lwn.net, peterz@infradead.org, arnd@arndb.de, punit.agrawal@bytedance.com, linux-kernel@vger.kernel.org, darren@os.amperecomputing.com, yangyicong@hisilicon.com, huzhanyuan@oppo.com, lipeifeng@oppo.com, zhangshiming@oppo.com, guojian@oppo.com, realmz6@gmail.com, linux-mips@vger.kernel.org, openrisc@lists.librecores.org, linuxppc-dev@lists.ozlabs.org, linux-riscv@lists.infradead.org, linux-s390@vger.kernel.org, Barry Song <21cnbao@gmail.com>, wangkefeng.wang@huawei.com, xhao@linux.alibaba.com, prime.zeng@hisilicon.com, Barry Song , Nadav Amit , Mel Gorman Subject: Re: [PATCH v7 2/2] arm64: support batched/deferred tlb shootdown during page reclamation Message-ID: References: <20221117082648.47526-1-yangyicong@huawei.com> <20221117082648.47526-3-yangyicong@huawei.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20221117082648.47526-3-yangyicong@huawei.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230105_101509_204010_A9B48938 X-CRM114-Status: GOOD ( 23.87 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Thu, Nov 17, 2022 at 04:26:48PM +0800, Yicong Yang wrote: > It is tested on 4,8,128 CPU platforms and shows to be beneficial on > large systems but may not have improvement on small systems like on > a 4 CPU platform. So make ARCH_WANT_BATCHED_UNMAP_TLB_FLUSH depends > on CONFIG_EXPERT for this stage and make this disabled on systems > with less than 8 CPUs. User can modify this threshold according to > their own platforms by CONFIG_NR_CPUS_FOR_BATCHED_TLB. What's the overhead of such batching on systems with 4 or fewer CPUs? If it isn't noticeable, I'd rather have it always on than some number chosen on whichever SoC you tested. Another option would be to make this a sysctl tunable. > .../features/vm/TLB/arch-support.txt | 2 +- > arch/arm64/Kconfig | 6 +++ > arch/arm64/include/asm/tlbbatch.h | 12 +++++ > arch/arm64/include/asm/tlbflush.h | 52 ++++++++++++++++++- > arch/x86/include/asm/tlbflush.h | 5 +- > include/linux/mm_types_task.h | 4 +- > mm/rmap.c | 10 ++-- Please keep any function prototype changes in a preparatory patch so that the arm64 one only introduces the arch specific changes. Easier to review. > +static inline bool arch_tlbbatch_should_defer(struct mm_struct *mm) > +{ > + /* > + * TLB batched flush is proved to be beneficial for systems with large > + * number of CPUs, especially system with more than 8 CPUs. TLB shutdown > + * is cheap on small systems which may not need this feature. So use > + * a threshold for enabling this to avoid potential side effects on > + * these platforms. > + */ > + if (num_online_cpus() < CONFIG_ARM64_NR_CPUS_FOR_BATCHED_TLB) > + return false; The x86 implementation tracks the cpumask of where a task has run. We don't have such tracking on arm64 and I don't think it matters. As noticed/described in this series, the bottleneck is the actual DSB synchronisation (which sends a DVM Sync message to all the other CPUs and waits for a DVM Complete response). So I think it makes sense not to bother with an mm_cpumask(). What this patch aims to optimise is actually the number of DSBs issued on an SMP system by ptep_clear_flush(). The DVM is not an architected concept (well, it's part of AMBA AXI). I'd be curious to know how such patch behaves on Apple's M1/M2 hardware. My preference would be to have this always on for num_online_cpus() > 1 if there's no overhead. -- Catalin _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel