From mboxrd@z Thu Jan 1 00:00:00 1970 From: Jisheng Zhang Date: Sun, 15 Jan 2023 21:59:18 +0800 Subject: [PATCH v3 05/13] riscv: cpufeature: extend riscv_cpufeature_patch_func to all ISA extensions In-Reply-To: <20230112092136.f2g43hrhmrqouy4y@orel> References: <20230111171027.2392-1-jszhang@kernel.org> <20230111171027.2392-6-jszhang@kernel.org> <2398293.3Lj2Plt8kZ@diego> <20230112092136.f2g43hrhmrqouy4y@orel> Message-ID: List-Id: To: kvm-riscv@lists.infradead.org MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit On Thu, Jan 12, 2023 at 10:21:36AM +0100, Andrew Jones wrote: > On Thu, Jan 12, 2023 at 12:29:57AM +0100, Heiko St?bner wrote: > > Hi Jisheng. > > > > Am Mittwoch, 11. Januar 2023, 18:10:19 CET schrieb Jisheng Zhang: > > > riscv_cpufeature_patch_func() currently only scans a limited set of > > > cpufeatures, explicitly defined with macros. Extend it to probe for all > > > ISA extensions. > > > > > > Signed-off-by: Jisheng Zhang > > > Reviewed-by: Andrew Jones > > > Reviewed-by: Heiko Stuebner > > > --- > > > arch/riscv/include/asm/errata_list.h | 9 ++-- > > > arch/riscv/kernel/cpufeature.c | 63 ++++------------------------ > > > 2 files changed, 11 insertions(+), 61 deletions(-) > > > > hmmm ... I do see a somewhat big caveat for this. > > and would like to take back my Reviewed-by for now > > > > > > With this change we would limit the patchable cpufeatures to actual > > riscv extensions. But cpufeatures can also be soft features like > > how performant the core handles unaligned accesses. > > I agree that this needs to be addressed and Jisheng also raised this > yesterday here [*]. It seems we need the concept of cpufeatures, which > may be extensions or non-extensions. > > [*] https://lore.kernel.org/all/Y77xyNPNqnFQUqAx at xhacker/ > > > > > See Palmer's series [0]. > > > > > > Also this essentially codifies that each ALTERNATIVE can only ever > > be attached to exactly one extension. > > > > But contrary to vendor-errata, it is very likely that we will need > > combinations of different extensions for some alternatives in the future. > > One possible approach may be to combine extensions/non-extensions at boot > time into pseudo-cpufeatures. Then, alternatives can continue attaching to > a single "feature". (I'm not saying that's a better approach than the > bitmap, I'm just suggesting it as something else to consider.) When swtiching pgtable_l4_enabled to static key for the first time, I suggested bitmap for cpufeatures which cover both ISA extensions and non-extensions-but-some-cpu-related-features [1], but it was rejected at that time, it seems we need to revisit the idea. [1] https://lore.kernel.org/linux-riscv/20220508160749.984-1-jszhang at kernel.org/ > > Thanks, > drew > > > > > In my optimization quest, I found that it's actually pretty neat to > > convert the errata-id for cpufeatures to a bitfield [1], because then it's > > possible to just combine extensions into said bitfield [2]: > > > > ALTERNATIVE_2("nop", > > "j strcmp_zbb_unaligned", 0, CPUFEATURE_ZBB | CPUFEATURE_FAST_UNALIGNED, 0, CONFIG_RISCV_ISA_ZBB, > > "j variant_zbb", 0, CPUFEATURE_ZBB, CPUFEATURE_FAST_UNALIGNED, CONFIG_RISCV_ISA_ZBB) > > > > [the additional field there models a "not" component] > > > > So I really feel this would limit us quite a bit. > > > > > > Heiko > > > > > > > > [0] https://git.kernel.org/pub/scm/linux/kernel/git/palmer/linux.git/commit/?h=riscv-hwprobe-v1&id=510c491cb9d87dcbdc91c63558dc704968723240 > > [1] https://github.com/mmind/linux-riscv/commit/f57a896122ee7e666692079320fc35829434cf96 > > [2] https://github.com/mmind/linux-riscv/commit/8cef615dab0c00ad68af2651ee5b93d06be17f27#diff-194cb8a86f9fb9b03683295f21c8f46b456a9f94737f01726ddbcbb9e3aace2cR12 > > > > From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 438FBC46467 for ; Sun, 15 Jan 2023 14:10:00 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:Cc:To:From:Date:Reply-To:Content-ID:Content-Description: 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client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id C7BE960C4D; Sun, 15 Jan 2023 14:09:41 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 72E1AC433D2; Sun, 15 Jan 2023 14:09:38 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1673791781; bh=zRcvm8EavOwpoEQYu0yKJXbKuP4uobFu5WALEjpcP2A=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=Me+1CzjEHuvOGX9tmzeZvwmy5/Ye7+OtsoY4qhSzsvUluuntBMZ1kbsKyo4DZkpv3 8LHx+kzUAMUd4Qf9yUJsCRPG4RRXxmVooWzr3jOMA7UMr9lLUMW1PS4dopDMxkqj7+ 3BnGofdmns+q2gJnKMgd2iZXZ1dyoW9UAr2jg1Q2dbcGvNNI928OF+pyKGTt36uH4C AngzjQTQ+bFdxQiADUiLXSWnX41/QS4YDGosNavH1BjHb14X8wkAcu2Aubbl2irbVf 6rwBBW/RzYJPNHDltGMPBlWbutzQHG2jrHhr50PyytTzgwrrC08aejhj3HEDL3XZ/d oqcEZFVj7mDWw== Date: Sun, 15 Jan 2023 21:59:18 +0800 From: Jisheng Zhang To: Andrew Jones Cc: Heiko =?utf-8?Q?St=C3=BCbner?= , Paul Walmsley , Palmer Dabbelt , Albert Ou , Anup Patel , Atish Patra , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org Subject: Re: [PATCH v3 05/13] riscv: cpufeature: extend riscv_cpufeature_patch_func to all ISA extensions Message-ID: References: <20230111171027.2392-1-jszhang@kernel.org> <20230111171027.2392-6-jszhang@kernel.org> <2398293.3Lj2Plt8kZ@diego> <20230112092136.f2g43hrhmrqouy4y@orel> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20230112092136.f2g43hrhmrqouy4y@orel> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230115_060942_551944_4391E63A X-CRM114-Status: GOOD ( 28.07 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Sender: "linux-riscv" Errors-To: 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id 72E1AC433D2; Sun, 15 Jan 2023 14:09:38 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1673791781; bh=zRcvm8EavOwpoEQYu0yKJXbKuP4uobFu5WALEjpcP2A=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=Me+1CzjEHuvOGX9tmzeZvwmy5/Ye7+OtsoY4qhSzsvUluuntBMZ1kbsKyo4DZkpv3 8LHx+kzUAMUd4Qf9yUJsCRPG4RRXxmVooWzr3jOMA7UMr9lLUMW1PS4dopDMxkqj7+ 3BnGofdmns+q2gJnKMgd2iZXZ1dyoW9UAr2jg1Q2dbcGvNNI928OF+pyKGTt36uH4C AngzjQTQ+bFdxQiADUiLXSWnX41/QS4YDGosNavH1BjHb14X8wkAcu2Aubbl2irbVf 6rwBBW/RzYJPNHDltGMPBlWbutzQHG2jrHhr50PyytTzgwrrC08aejhj3HEDL3XZ/d oqcEZFVj7mDWw== Date: Sun, 15 Jan 2023 21:59:18 +0800 From: Jisheng Zhang To: Andrew Jones Cc: Heiko =?utf-8?Q?St=C3=BCbner?= , Paul Walmsley , Palmer Dabbelt , Albert Ou , Anup Patel , Atish Patra , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org Subject: Re: [PATCH v3 05/13] riscv: cpufeature: extend riscv_cpufeature_patch_func to all ISA extensions Message-ID: References: <20230111171027.2392-1-jszhang@kernel.org> <20230111171027.2392-6-jszhang@kernel.org> <2398293.3Lj2Plt8kZ@diego> <20230112092136.f2g43hrhmrqouy4y@orel> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20230112092136.f2g43hrhmrqouy4y@orel> Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org On Thu, Jan 12, 2023 at 10:21:36AM +0100, Andrew Jones wrote: > On Thu, Jan 12, 2023 at 12:29:57AM +0100, Heiko Stübner wrote: > > Hi Jisheng. > > > > Am Mittwoch, 11. Januar 2023, 18:10:19 CET schrieb Jisheng Zhang: > > > riscv_cpufeature_patch_func() currently only scans a limited set of > > > cpufeatures, explicitly defined with macros. Extend it to probe for all > > > ISA extensions. > > > > > > Signed-off-by: Jisheng Zhang > > > Reviewed-by: Andrew Jones > > > Reviewed-by: Heiko Stuebner > > > --- > > > arch/riscv/include/asm/errata_list.h | 9 ++-- > > > arch/riscv/kernel/cpufeature.c | 63 ++++------------------------ > > > 2 files changed, 11 insertions(+), 61 deletions(-) > > > > hmmm ... I do see a somewhat big caveat for this. > > and would like to take back my Reviewed-by for now > > > > > > With this change we would limit the patchable cpufeatures to actual > > riscv extensions. But cpufeatures can also be soft features like > > how performant the core handles unaligned accesses. > > I agree that this needs to be addressed and Jisheng also raised this > yesterday here [*]. It seems we need the concept of cpufeatures, which > may be extensions or non-extensions. > > [*] https://lore.kernel.org/all/Y77xyNPNqnFQUqAx@xhacker/ > > > > > See Palmer's series [0]. > > > > > > Also this essentially codifies that each ALTERNATIVE can only ever > > be attached to exactly one extension. > > > > But contrary to vendor-errata, it is very likely that we will need > > combinations of different extensions for some alternatives in the future. > > One possible approach may be to combine extensions/non-extensions at boot > time into pseudo-cpufeatures. Then, alternatives can continue attaching to > a single "feature". (I'm not saying that's a better approach than the > bitmap, I'm just suggesting it as something else to consider.) When swtiching pgtable_l4_enabled to static key for the first time, I suggested bitmap for cpufeatures which cover both ISA extensions and non-extensions-but-some-cpu-related-features [1], but it was rejected at that time, it seems we need to revisit the idea. [1] https://lore.kernel.org/linux-riscv/20220508160749.984-1-jszhang@kernel.org/ > > Thanks, > drew > > > > > In my optimization quest, I found that it's actually pretty neat to > > convert the errata-id for cpufeatures to a bitfield [1], because then it's > > possible to just combine extensions into said bitfield [2]: > > > > ALTERNATIVE_2("nop", > > "j strcmp_zbb_unaligned", 0, CPUFEATURE_ZBB | CPUFEATURE_FAST_UNALIGNED, 0, CONFIG_RISCV_ISA_ZBB, > > "j variant_zbb", 0, CPUFEATURE_ZBB, CPUFEATURE_FAST_UNALIGNED, CONFIG_RISCV_ISA_ZBB) > > > > [the additional field there models a "not" component] > > > > So I really feel this would limit us quite a bit. > > > > > > Heiko > > > > > > > > [0] https://git.kernel.org/pub/scm/linux/kernel/git/palmer/linux.git/commit/?h=riscv-hwprobe-v1&id=510c491cb9d87dcbdc91c63558dc704968723240 > > [1] https://github.com/mmind/linux-riscv/commit/f57a896122ee7e666692079320fc35829434cf96 > > [2] https://github.com/mmind/linux-riscv/commit/8cef615dab0c00ad68af2651ee5b93d06be17f27#diff-194cb8a86f9fb9b03683295f21c8f46b456a9f94737f01726ddbcbb9e3aace2cR12 > > > >