From mboxrd@z Thu Jan 1 00:00:00 1970 From: Jisheng Zhang Date: Sun, 15 Jan 2023 22:19:36 +0800 Subject: [PATCH v3 05/13] riscv: cpufeature: extend riscv_cpufeature_patch_func to all ISA extensions In-Reply-To: <2398293.3Lj2Plt8kZ@diego> References: <20230111171027.2392-1-jszhang@kernel.org> <20230111171027.2392-6-jszhang@kernel.org> <2398293.3Lj2Plt8kZ@diego> Message-ID: List-Id: To: kvm-riscv@lists.infradead.org MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit On Thu, Jan 12, 2023 at 12:29:57AM +0100, Heiko St?bner wrote: > Hi Jisheng. Hi Heiko, > > Am Mittwoch, 11. Januar 2023, 18:10:19 CET schrieb Jisheng Zhang: > > riscv_cpufeature_patch_func() currently only scans a limited set of > > cpufeatures, explicitly defined with macros. Extend it to probe for all > > ISA extensions. > > > > Signed-off-by: Jisheng Zhang > > Reviewed-by: Andrew Jones > > Reviewed-by: Heiko Stuebner > > --- > > arch/riscv/include/asm/errata_list.h | 9 ++-- > > arch/riscv/kernel/cpufeature.c | 63 ++++------------------------ > > 2 files changed, 11 insertions(+), 61 deletions(-) > > hmmm ... I do see a somewhat big caveat for this. > and would like to take back my Reviewed-by for now > > > With this change we would limit the patchable cpufeatures to actual > riscv extensions. But cpufeatures can also be soft features like > how performant the core handles unaligned accesses. Besides Drew's comments and my reply a few minutes ago, here are what I thought: I agree with you about "cpufeatures can also be soft features" which I called cpu related features, but currently we don't have that case in urgent, the SV48 and SV57 are extensions now as Jessica pointed out[1], so I planed to send a v7 to apply the alternative mechanism for SV48/SV57, and I think we still have time to revisit the "expanding cpufeatures to cover soft features". But that need to be addressed in another improvement series. [1] https://lore.kernel.org/linux-riscv/391AFCB9-D314-4243-9E35-6D95B81C9400 at jrtc27.com/ > > See Palmer's series [0]. > > > Also this essentially codifies that each ALTERNATIVE can only ever > be attached to exactly one extension. > > But contrary to vendor-errata, it is very likely that we will need > combinations of different extensions for some alternatives in the future. > > In my optimization quest, I found that it's actually pretty neat to > convert the errata-id for cpufeatures to a bitfield [1], because then it's > possible to just combine extensions into said bitfield [2]: > > ALTERNATIVE_2("nop", > "j strcmp_zbb_unaligned", 0, CPUFEATURE_ZBB | CPUFEATURE_FAST_UNALIGNED, 0, CONFIG_RISCV_ISA_ZBB, > "j variant_zbb", 0, CPUFEATURE_ZBB, CPUFEATURE_FAST_UNALIGNED, CONFIG_RISCV_ISA_ZBB) > > [the additional field there models a "not" component] > > So I really feel this would limit us quite a bit. > > > Heiko > > > > [0] https://git.kernel.org/pub/scm/linux/kernel/git/palmer/linux.git/commit/?h=riscv-hwprobe-v1&id=510c491cb9d87dcbdc91c63558dc704968723240 > [1] https://github.com/mmind/linux-riscv/commit/f57a896122ee7e666692079320fc35829434cf96 > [2] https://github.com/mmind/linux-riscv/commit/8cef615dab0c00ad68af2651ee5b93d06be17f27#diff-194cb8a86f9fb9b03683295f21c8f46b456a9f94737f01726ddbcbb9e3aace2cR12 > > From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 2AF46C46467 for ; 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charset="utf-8" Content-Transfer-Encoding: base64 Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org T24gVGh1LCBKYW4gMTIsIDIwMjMgYXQgMTI6Mjk6NTdBTSArMDEwMCwgSGVpa28gU3TDvGJuZXIg d3JvdGU6Cj4gSGkgSmlzaGVuZy4KCkhpIEhlaWtvLAoKPiAKPiBBbSBNaXR0d29jaCwgMTEuIEph bnVhciAyMDIzLCAxODoxMDoxOSBDRVQgc2NocmllYiBKaXNoZW5nIFpoYW5nOgo+ID4gcmlzY3Zf Y3B1ZmVhdHVyZV9wYXRjaF9mdW5jKCkgY3VycmVudGx5IG9ubHkgc2NhbnMgYSBsaW1pdGVkIHNl dCBvZgo+ID4gY3B1ZmVhdHVyZXMsIGV4cGxpY2l0bHkgZGVmaW5lZCB3aXRoIG1hY3Jvcy4gRXh0 ZW5kIGl0IHRvIHByb2JlIGZvciBhbGwKPiA+IElTQSBleHRlbnNpb25zLgo+ID4gCj4gPiBTaWdu ZWQtb2ZmLWJ5OiBKaXNoZW5nIFpoYW5nIDxqc3poYW5nQGtlcm5lbC5vcmc+Cj4gPiBSZXZpZXdl ZC1ieTogQW5kcmV3IEpvbmVzIDxham9uZXNAdmVudGFuYW1pY3JvLmNvbT4KPiA+IFJldmlld2Vk LWJ5OiBIZWlrbyBTdHVlYm5lciA8aGVpa29Ac250ZWNoLmRlPgo+ID4gLS0tCj4gPiAgYXJjaC9y aXNjdi9pbmNsdWRlL2FzbS9lcnJhdGFfbGlzdC5oIHwgIDkgKystLQo+ID4gIGFyY2gvcmlzY3Yv a2VybmVsL2NwdWZlYXR1cmUuYyAgICAgICB8IDYzICsrKystLS0tLS0tLS0tLS0tLS0tLS0tLS0t LS0KPiA+ICAyIGZpbGVzIGNoYW5nZWQsIDExIGluc2VydGlvbnMoKyksIDYxIGRlbGV0aW9ucygt KQo+IAo+IGhtbW0gLi4uIEkgZG8gc2VlIGEgc29tZXdoYXQgYmlnIGNhdmVhdCBmb3IgdGhpcy4K PiBhbmQgd291bGQgbGlrZSB0byB0YWtlIGJhY2sgbXkgUmV2aWV3ZWQtYnkgZm9yIG5vdwo+IAo+ IAo+IFdpdGggdGhpcyBjaGFuZ2Ugd2Ugd291bGQgbGltaXQgdGhlIHBhdGNoYWJsZSBjcHVmZWF0 dXJlcyB0byBhY3R1YWwKPiByaXNjdiBleHRlbnNpb25zLiBCdXQgY3B1ZmVhdHVyZXMgY2FuIGFs c28gYmUgc29mdCBmZWF0dXJlcyBsaWtlCj4gaG93IHBlcmZvcm1hbnQgdGhlIGNvcmUgaGFuZGxl cyB1bmFsaWduZWQgYWNjZXNzZXMuCgpCZXNpZGVzIERyZXcncyBjb21tZW50cyBhbmQgbXkgcmVw bHkgYSBmZXcgbWludXRlcyBhZ28sIGhlcmUgYXJlCndoYXQgSSB0aG91Z2h0OiBJIGFncmVlIHdp dGggeW91IGFib3V0ICJjcHVmZWF0dXJlcyBjYW4gYWxzbyBiZSBzb2Z0CmZlYXR1cmVzIiB3aGlj aCBJIGNhbGxlZCBjcHUgcmVsYXRlZCBmZWF0dXJlcywgYnV0IGN1cnJlbnRseSB3ZQpkb24ndCBo YXZlIHRoYXQgY2FzZSBpbiB1cmdlbnQsIHRoZSBTVjQ4IGFuZCBTVjU3IGFyZSBleHRlbnNpb25z IG5vdwphcyBKZXNzaWNhIHBvaW50ZWQgb3V0WzFdLCBzbyBJIHBsYW5lZCB0byBzZW5kIGEgdjcg dG8gYXBwbHkgdGhlCmFsdGVybmF0aXZlIG1lY2hhbmlzbSBmb3IgU1Y0OC9TVjU3LCBhbmQgSSB0 aGluayB3ZSBzdGlsbCBoYXZlIHRpbWUgdG8KcmV2aXNpdCB0aGUgImV4cGFuZGluZyBjcHVmZWF0 dXJlcyB0byBjb3ZlciBzb2Z0IGZlYXR1cmVzIi4gQnV0IHRoYXQKbmVlZCB0byBiZSBhZGRyZXNz ZWQgaW4gYW5vdGhlciBpbXByb3ZlbWVudCBzZXJpZXMuCgpbMV0gaHR0cHM6Ly9sb3JlLmtlcm5l bC5vcmcvbGludXgtcmlzY3YvMzkxQUZDQjktRDMxNC00MjQzLTlFMzUtNkQ5NUI4MUM5NDAwQGpy dGMyNy5jb20vCgo+IAo+IFNlZSBQYWxtZXIncyBzZXJpZXMgWzBdLgo+IAo+IAo+IEFsc28gdGhp cyBlc3NlbnRpYWxseSBjb2RpZmllcyB0aGF0IGVhY2ggQUxURVJOQVRJVkUgY2FuIG9ubHkgZXZl cgo+IGJlIGF0dGFjaGVkIHRvIGV4YWN0bHkgb25lIGV4dGVuc2lvbi4KPiAKPiBCdXQgY29udHJh cnkgdG8gdmVuZG9yLWVycmF0YSwgaXQgaXMgdmVyeSBsaWtlbHkgdGhhdCB3ZSB3aWxsIG5lZWQK PiBjb21iaW5hdGlvbnMgb2YgZGlmZmVyZW50IGV4dGVuc2lvbnMgZm9yIHNvbWUgYWx0ZXJuYXRp dmVzIGluIHRoZSBmdXR1cmUuCj4gCj4gSW4gbXkgb3B0aW1pemF0aW9uIHF1ZXN0LCBJIGZvdW5k IHRoYXQgaXQncyBhY3R1YWxseSBwcmV0dHkgbmVhdCB0bwo+IGNvbnZlcnQgdGhlIGVycmF0YS1p ZCBmb3IgY3B1ZmVhdHVyZXMgdG8gYSBiaXRmaWVsZCBbMV0sIGJlY2F1c2UgdGhlbiBpdCdzCj4g cG9zc2libGUgdG8ganVzdCBjb21iaW5lIGV4dGVuc2lvbnMgaW50byBzYWlkIGJpdGZpZWxkIFsy XToKPiAKPiAJQUxURVJOQVRJVkVfMigibm9wIiwKPiAJCSAgICAgICJqIHN0cmNtcF96YmJfdW5h bGlnbmVkIiwgMCwgQ1BVRkVBVFVSRV9aQkIgfCBDUFVGRUFUVVJFX0ZBU1RfVU5BTElHTkVELCAw LCBDT05GSUdfUklTQ1ZfSVNBX1pCQiwKPiAJCSAgICAgICJqIHZhcmlhbnRfemJiIiwgMCwgQ1BV RkVBVFVSRV9aQkIsIENQVUZFQVRVUkVfRkFTVF9VTkFMSUdORUQsIENPTkZJR19SSVNDVl9JU0Ff WkJCKQo+IAo+IFt0aGUgYWRkaXRpb25hbCBmaWVsZCB0aGVyZSBtb2RlbHMgYSAibm90IiBjb21w b25lbnRdCj4gCj4gU28gSSByZWFsbHkgZmVlbCB0aGlzIHdvdWxkIGxpbWl0IHVzIHF1aXRlIGEg Yml0Lgo+IAo+IAo+IEhlaWtvCj4gCj4gCj4gCj4gWzBdIGh0dHBzOi8vZ2l0Lmtlcm5lbC5vcmcv cHViL3NjbS9saW51eC9rZXJuZWwvZ2l0L3BhbG1lci9saW51eC5naXQvY29tbWl0Lz9oPXJpc2N2 LWh3cHJvYmUtdjEmaWQ9NTEwYzQ5MWNiOWQ4N2RjYmRjOTFjNjM1NThkYzcwNDk2ODcyMzI0MAo+ IFsxXSBodHRwczovL2dpdGh1Yi5jb20vbW1pbmQvbGludXgtcmlzY3YvY29tbWl0L2Y1N2E4OTYx MjJlZTdlNjY2NjkyMDc5MzIwZmMzNTgyOTQzNGNmOTYKPiBbMl0gaHR0cHM6Ly9naXRodWIuY29t L21taW5kL2xpbnV4LXJpc2N2L2NvbW1pdC84Y2VmNjE1ZGFiMGMwMGFkNjhhZjI2NTFlZTViOTNk MDZiZTE3ZjI3I2RpZmYtMTk0Y2I4YTg2ZjlmYjliMDM2ODMyOTVmMjFjOGY0NmI0NTZhOWY5NDcz N2YwMTcyNmRkYmNiYjllM2FhY2UyY1IxMgo+IAo+IAoKX19fX19fX19fX19fX19fX19fX19fX19f X19fX19fX19fX19fX19fX19fX19fX18KbGludXgtcmlzY3YgbWFpbGluZyBsaXN0CmxpbnV4LXJp c2N2QGxpc3RzLmluZnJhZGVhZC5vcmcKaHR0cDovL2xpc3RzLmluZnJhZGVhZC5vcmcvbWFpbG1h bi9saXN0aW5mby9saW51eC1yaXNjdgo= From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2DBA8C46467 for ; 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d=kernel.org; s=k20201202; t=1673792995; bh=6AtmHzTmKwhgZfSkJiaOs9M/vE83edxq/5rI8jWJTDA=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=G9UJrY4MuohrZre8aaAvWuiPtSMtKDoZMZQugcSnhN33c0oVIS2CkMhkPMag0lFfA mrne9FkOTKLJvEl5VbFlH0KqL3CV6ZlDK3hKasVUIxs7qE1J7od5a1PNTNFMe8qUdU bPD1ul6caPZogks//5UiMuMHNXoeKncnrZzJC938evyfwJpycJ9koF+7d33TX6A3q1 s/xtQjUMRzSORolZuBW8zDCEQ3AaHLN9OjC6RsxEg026KbrB8GUXWvzSzEUmkZVSvH CcQZtStB/G92s5SjEQ63G7vGIkHQrgZTagnz57uP+3Hm6+xr1TpfJ4TOVndH2/UO1V VtMKEKArJjMag== Date: Sun, 15 Jan 2023 22:19:36 +0800 From: Jisheng Zhang To: Heiko =?utf-8?Q?St=C3=BCbner?= Cc: Paul Walmsley , Palmer Dabbelt , Albert Ou , Anup Patel , Atish Patra , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, Andrew Jones Subject: Re: [PATCH v3 05/13] riscv: cpufeature: extend riscv_cpufeature_patch_func to all ISA extensions Message-ID: References: <20230111171027.2392-1-jszhang@kernel.org> <20230111171027.2392-6-jszhang@kernel.org> <2398293.3Lj2Plt8kZ@diego> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <2398293.3Lj2Plt8kZ@diego> Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org On Thu, Jan 12, 2023 at 12:29:57AM +0100, Heiko Stübner wrote: > Hi Jisheng. Hi Heiko, > > Am Mittwoch, 11. Januar 2023, 18:10:19 CET schrieb Jisheng Zhang: > > riscv_cpufeature_patch_func() currently only scans a limited set of > > cpufeatures, explicitly defined with macros. Extend it to probe for all > > ISA extensions. > > > > Signed-off-by: Jisheng Zhang > > Reviewed-by: Andrew Jones > > Reviewed-by: Heiko Stuebner > > --- > > arch/riscv/include/asm/errata_list.h | 9 ++-- > > arch/riscv/kernel/cpufeature.c | 63 ++++------------------------ > > 2 files changed, 11 insertions(+), 61 deletions(-) > > hmmm ... I do see a somewhat big caveat for this. > and would like to take back my Reviewed-by for now > > > With this change we would limit the patchable cpufeatures to actual > riscv extensions. But cpufeatures can also be soft features like > how performant the core handles unaligned accesses. Besides Drew's comments and my reply a few minutes ago, here are what I thought: I agree with you about "cpufeatures can also be soft features" which I called cpu related features, but currently we don't have that case in urgent, the SV48 and SV57 are extensions now as Jessica pointed out[1], so I planed to send a v7 to apply the alternative mechanism for SV48/SV57, and I think we still have time to revisit the "expanding cpufeatures to cover soft features". But that need to be addressed in another improvement series. [1] https://lore.kernel.org/linux-riscv/391AFCB9-D314-4243-9E35-6D95B81C9400@jrtc27.com/ > > See Palmer's series [0]. > > > Also this essentially codifies that each ALTERNATIVE can only ever > be attached to exactly one extension. > > But contrary to vendor-errata, it is very likely that we will need > combinations of different extensions for some alternatives in the future. > > In my optimization quest, I found that it's actually pretty neat to > convert the errata-id for cpufeatures to a bitfield [1], because then it's > possible to just combine extensions into said bitfield [2]: > > ALTERNATIVE_2("nop", > "j strcmp_zbb_unaligned", 0, CPUFEATURE_ZBB | CPUFEATURE_FAST_UNALIGNED, 0, CONFIG_RISCV_ISA_ZBB, > "j variant_zbb", 0, CPUFEATURE_ZBB, CPUFEATURE_FAST_UNALIGNED, CONFIG_RISCV_ISA_ZBB) > > [the additional field there models a "not" component] > > So I really feel this would limit us quite a bit. > > > Heiko > > > > [0] https://git.kernel.org/pub/scm/linux/kernel/git/palmer/linux.git/commit/?h=riscv-hwprobe-v1&id=510c491cb9d87dcbdc91c63558dc704968723240 > [1] https://github.com/mmind/linux-riscv/commit/f57a896122ee7e666692079320fc35829434cf96 > [2] https://github.com/mmind/linux-riscv/commit/8cef615dab0c00ad68af2651ee5b93d06be17f27#diff-194cb8a86f9fb9b03683295f21c8f46b456a9f94737f01726ddbcbb9e3aace2cR12 > >