diff for duplicates of <Y8hwHbvtgw5bW3lC@spud>

diff --git a/N1/1.1.hdr b/N1/1.1.hdr
new file mode 100644
index 0000000..5a32186
--- /dev/null
+++ b/N1/1.1.hdr
@@ -0,0 +1,3 @@
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+Content-Disposition: inline
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diff --git a/a/1.txt b/N1/1.1.txt
similarity index 89%
rename from a/1.txt
rename to N1/1.1.txt
index 12866fc..0088bd4 100644
--- a/a/1.txt
+++ b/N1/1.1.txt
@@ -28,8 +28,8 @@ On Sun, Jan 15, 2023 at 11:49:46PM +0800, Jisheng Zhang wrote:
 > are patched using alternatives, thus the metadata can be freed after
 > patching.
 > 
-> Link: https://lore.kernel.org/linux-riscv/20220922060958.44203-1-samuel at sholland.org/ [1]
-> Link: https://lore.kernel.org/linux-arm-kernel/20220912162210.3626215-8-mark.rutland at arm.com/ [2]
+> Link: https://lore.kernel.org/linux-riscv/20220922060958.44203-1-samuel@sholland.org/ [1]
+> Link: https://lore.kernel.org/linux-arm-kernel/20220912162210.3626215-8-mark.rutland@arm.com/ [2]
 > Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
 > Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
 
@@ -40,7 +40,7 @@ that we're not just introducing something that'd conflict with trying
 to use this mechanism for non-extension capabilities:
 Acked-by: Conor Dooley <conor.dooley@microchip.com>
 
-1 - https://lore.kernel.org/linux-riscv/Y8hqptFcUgjhns4F at spud/
+1 - https://lore.kernel.org/linux-riscv/Y8hqptFcUgjhns4F@spud/
 > ---
 >  arch/riscv/include/asm/hwcap.h | 37 ++++++++++++++++++++++++++++++++++
 >  1 file changed, 37 insertions(+)
@@ -106,12 +106,5 @@ Acked-by: Conor Dooley <conor.dooley@microchip.com>
 > 
 > _______________________________________________
 > linux-riscv mailing list
-> linux-riscv at lists.infradead.org
+> linux-riscv@lists.infradead.org
 > http://lists.infradead.org/mailman/listinfo/linux-riscv
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diff --git a/N1/1.2.bin b/N1/1.2.bin
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diff --git a/N1/2.hdr b/N1/2.hdr
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diff --git a/N1/2.txt b/N1/2.txt
new file mode 100644
index 0000000..e409076
--- /dev/null
+++ b/N1/2.txt
@@ -0,0 +1,4 @@
+_______________________________________________
+linux-riscv mailing list
+linux-riscv@lists.infradead.org
+http://lists.infradead.org/mailman/listinfo/linux-riscv
diff --git a/a/content_digest b/N1/content_digest
index d5fda2d..c4c5e3b 100644
--- a/a/content_digest
+++ b/N1/content_digest
@@ -1,10 +1,22 @@
  "ref\020230115154953.831-1-jszhang@kernel.org\0"
  "ref\020230115154953.831-7-jszhang@kernel.org\0"
  "From\0Conor Dooley <conor@kernel.org>\0"
- "Subject\0[PATCH v4 06/13] riscv: introduce riscv_has_extension_[un]likely()\0"
+ "Subject\0Re: [PATCH v4 06/13] riscv: introduce riscv_has_extension_[un]likely()\0"
  "Date\0Wed, 18 Jan 2023 22:18:05 +0000\0"
- "To\0kvm-riscv@lists.infradead.org\0"
- "\00:1\0"
+ "To\0Jisheng Zhang <jszhang@kernel.org>\0"
+ "Cc\0Paul Walmsley <paul.walmsley@sifive.com>"
+  Palmer Dabbelt <palmer@dabbelt.com>
+  Albert Ou <aou@eecs.berkeley.edu>
+  Anup Patel <anup@brainfault.org>
+  Atish Patra <atishp@atishpatra.org>
+  Heiko Stuebner <heiko@sntech.de>
+  Conor Dooley <conor.dooley@microchip.com>
+  Andrew Jones <ajones@ventanamicro.com>
+  linux-riscv@lists.infradead.org
+  linux-kernel@vger.kernel.org
+  kvm@vger.kernel.org
+ " kvm-riscv@lists.infradead.org\0"
+ "\02:1.1\0"
  "b\0"
  "On Sun, Jan 15, 2023 at 11:49:46PM +0800, Jisheng Zhang wrote:\n"
  "> Generally, riscv ISA extensions are fixed for any specific hardware\n"
@@ -36,8 +48,8 @@
  "> are patched using alternatives, thus the metadata can be freed after\n"
  "> patching.\n"
  "> \n"
- "> Link: https://lore.kernel.org/linux-riscv/20220922060958.44203-1-samuel at sholland.org/ [1]\n"
- "> Link: https://lore.kernel.org/linux-arm-kernel/20220912162210.3626215-8-mark.rutland at arm.com/ [2]\n"
+ "> Link: https://lore.kernel.org/linux-riscv/20220922060958.44203-1-samuel@sholland.org/ [1]\n"
+ "> Link: https://lore.kernel.org/linux-arm-kernel/20220912162210.3626215-8-mark.rutland@arm.com/ [2]\n"
  "> Signed-off-by: Jisheng Zhang <jszhang@kernel.org>\n"
  "> Reviewed-by: Andrew Jones <ajones@ventanamicro.com>\n"
  "\n"
@@ -48,7 +60,7 @@
  "to use this mechanism for non-extension capabilities:\n"
  "Acked-by: Conor Dooley <conor.dooley@microchip.com>\n"
  "\n"
- "1 - https://lore.kernel.org/linux-riscv/Y8hqptFcUgjhns4F at spud/\n"
+ "1 - https://lore.kernel.org/linux-riscv/Y8hqptFcUgjhns4F@spud/\n"
  "> ---\n"
  ">  arch/riscv/include/asm/hwcap.h | 37 ++++++++++++++++++++++++++++++++++\n"
  ">  1 file changed, 37 insertions(+)\n"
@@ -114,14 +126,23 @@
  "> \n"
  "> _______________________________________________\n"
  "> linux-riscv mailing list\n"
- "> linux-riscv at lists.infradead.org\n"
- "> http://lists.infradead.org/mailman/listinfo/linux-riscv\n"
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+ "> linux-riscv@lists.infradead.org\n"
+ > http://lists.infradead.org/mailman/listinfo/linux-riscv
+ "\02:1.2\0"
+ "fn\0signature.asc\0"
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+ "b\0"
+ "_______________________________________________\n"
+ "linux-riscv mailing list\n"
+ "linux-riscv@lists.infradead.org\n"
+ http://lists.infradead.org/mailman/listinfo/linux-riscv
 
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