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DIR:OUT; SFP:1102; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?us-ascii?Q?FRr2StABxbvazcNa7Sl3k5/873jlbjGXgCWVFZHclhREJKKTaFBXqp5cvGRG?= =?us-ascii?Q?L8ZEp/7VL4MzSVa0Die+dK+qUSrbAsS3hntSotEZdS6OWwSR+jXKvbtyKGRQ?= =?us-ascii?Q?LrLWi7bLr51p9u4g1bNL5+xNpGd/T9vIX3UKBd4lsTfyLjIUYrAVtoogNcDC?= =?us-ascii?Q?4pnEXHLtdCldkh2vbU7/E+SsXhQiTkLS0c74RW8kFGlEVi/L4qqlRIIF6Gcd?= =?us-ascii?Q?Qwn+e7/2/NCOeY0H4Q/M0YTbZ3LIa+y8RxsrZiPlsPdTfaLfer6L9SjUhLj8?= =?us-ascii?Q?eJnEdN3tZ3Twstv1N+zrEmuYiFfEPnSnH62uYJkMVhdL8biNWwNu206uoNzw?= =?us-ascii?Q?pROvdhILMpZJniPJOucYwV5/hrkNx89DWxFOg4FBDNoTwnOhiyhgK883QAiQ?= =?us-ascii?Q?XwarL3beI4u75Q2vGau1M7zthJqVfO74nEyeml/6/L8z2zbirNekc1MQFvhF?= =?us-ascii?Q?An8BAIrYPMWLmIW1P+3irBf/lq7/gkAIleDkQcChzK5r4mCd9bQHs9Q8xFO0?= =?us-ascii?Q?DPWCSU/GmwNlVeD0JyhHblJEnIrYHKgRBGTRMTB0fXZLgYn+IJadnaWivz9n?= =?us-ascii?Q?dlTbw7PWTpgvNyZ3jgB/7k2tTkYUwOLZPjtoSkvSED41aClyULTRkXPn5dBe?= =?us-ascii?Q?WsZXf5zBEoFOYTqMNMvd3+yx+0nM027m7PsmJquxIzSzer9vLb9sg3wqvWbB?= =?us-ascii?Q?tdy0e4cXCVV6oipS/ihjYepnwJhfd2EzAmxZE+kpdsdkaIs6bGD9lOaEVFnZ?= =?us-ascii?Q?Tt3oiKNYC7jQQ3kzc2qOA3FB/+z4bnKfYPWjr5puwpiPZyVRwEbbiKOGnjxr?= =?us-ascii?Q?R755IM7rYVYQOI6Uc7c2wuNu9i8xQCduEimXGY+i/nwFHAuDUe1nrov0E5yC?= =?us-ascii?Q?OULfYWIl5Ro8hp1jekTHL//TZ4sPvVmFf9Vi0RczfZO+lFh+XUOPFr8jolMH?= =?us-ascii?Q?TxzQmYR+QTG92IZqEB5YGl7LxyQCL0a8+//dzG3FzanCDb5SpRg76d0qmUvA?= =?us-ascii?Q?V6ghfoqqOtFt1FOO8C9UjjDNehb+KZ15rPvq2uHADmR2kY52jtk+D30ji11L?= =?us-ascii?Q?78+cVWsIXQDEf4JB/e3MdY0wg7vNpl496hUy+/2uOoOXFn9Mf+KNVNNUxj+7?= =?us-ascii?Q?q5CAC56NOSj15Y1RtjX4MVyQ7Cg1MfdOv4Ie/0IR1pQPBUfe6OWujkaCaIA8?= =?us-ascii?Q?7bCr9ON9R2UZaQohdLEfWGScV08OkgwskjNtHzScBmvdzu23Cbt/d9QoujZb?= =?us-ascii?Q?YGKjdKcMoGx5YEoZaojlYbipgzisKAFR+EV9rqL751kWcL4ZPWG2Z9/roKPw?= =?us-ascii?Q?Xax7l/+60hlOWNU+eU6ThvYMdQpVHGHXFAhQEOYhrVlW3+ln6MlHxLsrHpRN?= =?us-ascii?Q?0Elgu+8q2muQ/rro6wVXGJ7JwMgQympjvRjdtMbqcWkh70PqfGPBcxsm44vY?= =?us-ascii?Q?WJl9N4nEbwmn5HeQsVJOOgzqU5skFZjIooOn0xmBSi/2uR9FRL/ASPdIYMHT?= =?us-ascii?Q?LAJ55nCTBjDd8RYkaTZmhQ7iu8Hj4SmEOfJalpPP53tj7UGMCfqc7cwyAJqm?= =?us-ascii?Q?ygYn+aWE+75Cu6gJTMQK+Y4MiRIIv1Yg8Zx9ZnrQVKr83i4h8bH0JgXDVy0f?= =?us-ascii?Q?Nw=3D=3D?= X-MS-Exchange-CrossTenant-Network-Message-Id: f92d973b-02b7-4fc3-7931-08dafa6817c6 X-MS-Exchange-CrossTenant-AuthSource: MN0PR11MB6059.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 Jan 2023 21:57:01.1582 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: DyHZRdooU6/JsubNiwdwq2iJnCrox/96PMQ95+sxiu2ZH2ogP0nXMdCik32qKg7KQWfXah3oqcBvTG7YtN1LTQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN9PR11MB5419 X-OriginatorOrg: intel.com Subject: Re: [Intel-gfx] [PATCH v2 1/2] drm/i915/doc: Document where to implement register workarounds X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: intel-gfx@lists.freedesktop.org Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" On Wed, Jan 18, 2023 at 12:52:48PM -0300, Gustavo Sousa wrote: > Extend the existing documentation in gt/intel_workarounds.c to make it > clear which functions register workarounds should be implemented in > according to their types. > > Signed-off-by: Gustavo Sousa Thank you Reviewed-by: Rodrigo Vivi > --- > drivers/gpu/drm/i915/gt/intel_workarounds.c | 16 ++++++++++++++++ > 1 file changed, 16 insertions(+) > > diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c > index 6dacd0dc5c2c..ef6065ce8267 100644 > --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c > +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c > @@ -30,6 +30,9 @@ > * creation to have a "primed golden context", i.e. a context image that > * already contains the changes needed to all the registers. > * > + * Context workarounds should be implemented in the *_ctx_workarounds_init() > + * variants respective to the targeted platforms. > + * > * - Engine workarounds: the list of these WAs is applied whenever the specific > * engine is reset. It's also possible that a set of engine classes share a > * common power domain and they are reset together. This happens on some > @@ -42,15 +45,28 @@ > * saves/restores their values before/after the reset takes place. See > * ``drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c`` for reference. > * > + * Workarounds for registers specific to RCS and CCS should be implemented in > + * rcs_engine_wa_init() and ccs_engine_wa_init(), respectively; those for > + * registers belonging to BCS, VCS or VECS should be implemented in > + * xcs_engine_wa_init(). Workarounds for registers not belonging to a specific > + * engine's MMIO range but that are part of of the common RCS/CCS reset domain > + * should be implemented in general_render_compute_wa_init(). > + * > * - GT workarounds: the list of these WAs is applied whenever these registers > * revert to their default values: on GPU reset, suspend/resume [1]_, etc. > * > + * GT workarounds should be implemented in the *_gt_workarounds_init() > + * variants respective to the targeted platforms. > + * > * - Register whitelist: some workarounds need to be implemented in userspace, > * but need to touch privileged registers. The whitelist in the kernel > * instructs the hardware to allow the access to happen. From the kernel side, > * this is just a special case of a MMIO workaround (as we write the list of > * these to/be-whitelisted registers to some special HW registers). > * > + * Register whitelisting should be done in the *_whitelist_build() variants > + * respective to the targeted platforms. > + * > * - Workaround batchbuffers: buffers that get executed automatically by the > * hardware on every HW context restore. These buffers are created and > * programmed in the default context so the hardware always go through those > -- > 2.39.0 >