* [Intel-gfx] [PATCH v2 0/2] drm/i915/gt: Move LSC_CHICKEN_BIT* workarounds to correct function (Series)
@ 2023-01-18 15:52 Gustavo Sousa
2023-01-18 15:52 ` [Intel-gfx] [PATCH v2 1/2] drm/i915/doc: Document where to implement register workarounds Gustavo Sousa
` (4 more replies)
0 siblings, 5 replies; 12+ messages in thread
From: Gustavo Sousa @ 2023-01-18 15:52 UTC (permalink / raw)
To: intel-gfx; +Cc: Rodrigo Vivi
This series as v2 of an originally single patch moving workarounds for
LSC_CHICKEN_BIT* registers into their correct function.
This version prepends a patch extending the existing documentation in
gt/intel_workarounds.c to make it clear where workarounds should be
implemented according to their type.
Gustavo Sousa (2):
drm/i915/doc: Document where to implement register workarounds
drm/i915/gt: Move LSC_CHICKEN_BIT* workarounds to correct function
drivers/gpu/drm/i915/gt/intel_workarounds.c | 81 +++++++++++++--------
1 file changed, 52 insertions(+), 29 deletions(-)
--
2.39.0
^ permalink raw reply [flat|nested] 12+ messages in thread* [Intel-gfx] [PATCH v2 1/2] drm/i915/doc: Document where to implement register workarounds 2023-01-18 15:52 [Intel-gfx] [PATCH v2 0/2] drm/i915/gt: Move LSC_CHICKEN_BIT* workarounds to correct function (Series) Gustavo Sousa @ 2023-01-18 15:52 ` Gustavo Sousa 2023-01-19 21:56 ` Rodrigo Vivi 2023-01-18 15:52 ` [Intel-gfx] [PATCH v2 2/2] drm/i915/gt: Move LSC_CHICKEN_BIT* workarounds to correct function Gustavo Sousa ` (3 subsequent siblings) 4 siblings, 1 reply; 12+ messages in thread From: Gustavo Sousa @ 2023-01-18 15:52 UTC (permalink / raw) To: intel-gfx; +Cc: Rodrigo Vivi Extend the existing documentation in gt/intel_workarounds.c to make it clear which functions register workarounds should be implemented in according to their types. Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com> --- drivers/gpu/drm/i915/gt/intel_workarounds.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c index 6dacd0dc5c2c..ef6065ce8267 100644 --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c @@ -30,6 +30,9 @@ * creation to have a "primed golden context", i.e. a context image that * already contains the changes needed to all the registers. * + * Context workarounds should be implemented in the *_ctx_workarounds_init() + * variants respective to the targeted platforms. + * * - Engine workarounds: the list of these WAs is applied whenever the specific * engine is reset. It's also possible that a set of engine classes share a * common power domain and they are reset together. This happens on some @@ -42,15 +45,28 @@ * saves/restores their values before/after the reset takes place. See * ``drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c`` for reference. * + * Workarounds for registers specific to RCS and CCS should be implemented in + * rcs_engine_wa_init() and ccs_engine_wa_init(), respectively; those for + * registers belonging to BCS, VCS or VECS should be implemented in + * xcs_engine_wa_init(). Workarounds for registers not belonging to a specific + * engine's MMIO range but that are part of of the common RCS/CCS reset domain + * should be implemented in general_render_compute_wa_init(). + * * - GT workarounds: the list of these WAs is applied whenever these registers * revert to their default values: on GPU reset, suspend/resume [1]_, etc. * + * GT workarounds should be implemented in the *_gt_workarounds_init() + * variants respective to the targeted platforms. + * * - Register whitelist: some workarounds need to be implemented in userspace, * but need to touch privileged registers. The whitelist in the kernel * instructs the hardware to allow the access to happen. From the kernel side, * this is just a special case of a MMIO workaround (as we write the list of * these to/be-whitelisted registers to some special HW registers). * + * Register whitelisting should be done in the *_whitelist_build() variants + * respective to the targeted platforms. + * * - Workaround batchbuffers: buffers that get executed automatically by the * hardware on every HW context restore. These buffers are created and * programmed in the default context so the hardware always go through those -- 2.39.0 ^ permalink raw reply related [flat|nested] 12+ messages in thread
* Re: [Intel-gfx] [PATCH v2 1/2] drm/i915/doc: Document where to implement register workarounds 2023-01-18 15:52 ` [Intel-gfx] [PATCH v2 1/2] drm/i915/doc: Document where to implement register workarounds Gustavo Sousa @ 2023-01-19 21:56 ` Rodrigo Vivi 0 siblings, 0 replies; 12+ messages in thread From: Rodrigo Vivi @ 2023-01-19 21:56 UTC (permalink / raw) To: Gustavo Sousa; +Cc: intel-gfx On Wed, Jan 18, 2023 at 12:52:48PM -0300, Gustavo Sousa wrote: > Extend the existing documentation in gt/intel_workarounds.c to make it > clear which functions register workarounds should be implemented in > according to their types. > > Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com> Thank you Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> > --- > drivers/gpu/drm/i915/gt/intel_workarounds.c | 16 ++++++++++++++++ > 1 file changed, 16 insertions(+) > > diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c > index 6dacd0dc5c2c..ef6065ce8267 100644 > --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c > +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c > @@ -30,6 +30,9 @@ > * creation to have a "primed golden context", i.e. a context image that > * already contains the changes needed to all the registers. > * > + * Context workarounds should be implemented in the *_ctx_workarounds_init() > + * variants respective to the targeted platforms. > + * > * - Engine workarounds: the list of these WAs is applied whenever the specific > * engine is reset. It's also possible that a set of engine classes share a > * common power domain and they are reset together. This happens on some > @@ -42,15 +45,28 @@ > * saves/restores their values before/after the reset takes place. See > * ``drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c`` for reference. > * > + * Workarounds for registers specific to RCS and CCS should be implemented in > + * rcs_engine_wa_init() and ccs_engine_wa_init(), respectively; those for > + * registers belonging to BCS, VCS or VECS should be implemented in > + * xcs_engine_wa_init(). Workarounds for registers not belonging to a specific > + * engine's MMIO range but that are part of of the common RCS/CCS reset domain > + * should be implemented in general_render_compute_wa_init(). > + * > * - GT workarounds: the list of these WAs is applied whenever these registers > * revert to their default values: on GPU reset, suspend/resume [1]_, etc. > * > + * GT workarounds should be implemented in the *_gt_workarounds_init() > + * variants respective to the targeted platforms. > + * > * - Register whitelist: some workarounds need to be implemented in userspace, > * but need to touch privileged registers. The whitelist in the kernel > * instructs the hardware to allow the access to happen. From the kernel side, > * this is just a special case of a MMIO workaround (as we write the list of > * these to/be-whitelisted registers to some special HW registers). > * > + * Register whitelisting should be done in the *_whitelist_build() variants > + * respective to the targeted platforms. > + * > * - Workaround batchbuffers: buffers that get executed automatically by the > * hardware on every HW context restore. These buffers are created and > * programmed in the default context so the hardware always go through those > -- > 2.39.0 > ^ permalink raw reply [flat|nested] 12+ messages in thread
* [Intel-gfx] [PATCH v2 2/2] drm/i915/gt: Move LSC_CHICKEN_BIT* workarounds to correct function 2023-01-18 15:52 [Intel-gfx] [PATCH v2 0/2] drm/i915/gt: Move LSC_CHICKEN_BIT* workarounds to correct function (Series) Gustavo Sousa 2023-01-18 15:52 ` [Intel-gfx] [PATCH v2 1/2] drm/i915/doc: Document where to implement register workarounds Gustavo Sousa @ 2023-01-18 15:52 ` Gustavo Sousa 2023-01-19 21:57 ` Rodrigo Vivi 2023-01-18 23:42 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/gt: Move LSC_CHICKEN_BIT* workarounds to correct function (Series) Patchwork ` (2 subsequent siblings) 4 siblings, 1 reply; 12+ messages in thread From: Gustavo Sousa @ 2023-01-18 15:52 UTC (permalink / raw) To: intel-gfx; +Cc: Rodrigo Vivi That register doesn't belong to a specific engine, so the proper placement for workarounds programming it should be general_render_compute_wa_init(). Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com> --- drivers/gpu/drm/i915/gt/intel_workarounds.c | 65 ++++++++++++--------- 1 file changed, 36 insertions(+), 29 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c index ef6065ce8267..918a271447e2 100644 --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c @@ -2341,10 +2341,6 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) /* Wa_1509727124 */ wa_mcr_masked_en(wal, GEN10_SAMPLER_MODE, SC_DISABLE_POWER_OPTIMIZATION_EBB); - - /* Wa_22013037850 */ - wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0_UDW, - DISABLE_128B_EVICTION_COMMAND_UDW); } if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_FOREVER) || @@ -2373,21 +2369,6 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) GEN12_DISABLE_HDR_PAST_PAYLOAD_HOLD_FIX); } - if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_C0) || - IS_DG2_G11(i915)) { - /* - * Wa_22012826095:dg2 - * Wa_22013059131:dg2 - */ - wa_mcr_write_clr_set(wal, LSC_CHICKEN_BIT_0_UDW, - MAXREQS_PER_BANK, - REG_FIELD_PREP(MAXREQS_PER_BANK, 2)); - - /* Wa_22013059131:dg2 */ - wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0, - FORCE_1_SUB_MESSAGE_PER_FRAGMENT); - } - /* Wa_1308578152:dg2_g10 when first gslice is fused off */ if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_C0) && needs_wa_1308578152(engine)) { @@ -2412,16 +2393,6 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) */ wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN, MDQ_ARBITRATION_MODE | UGM_BACKUP_MODE); - - /* - * Wa_14010918519:dg2_g10 - * - * LSC_CHICKEN_BIT_0 always reads back as 0 is this stepping, - * so ignoring verification. - */ - wa_mcr_add(wal, LSC_CHICKEN_BIT_0_UDW, 0, - FORCE_SLM_FENCE_SCOPE_TO_TILE | FORCE_UGM_FENCE_SCOPE_TO_TILE, - 0, false); } if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_A0, STEP_B0)) { @@ -3006,6 +2977,15 @@ general_render_compute_wa_init(struct intel_engine_cs *engine, struct i915_wa_li add_render_compute_tuning_settings(i915, wal); + if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) || + IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0) || + IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_FOREVER) || + IS_DG2_G11(i915) || IS_DG2_G12(i915)) { + /* Wa_22013037850 */ + wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0_UDW, + DISABLE_128B_EVICTION_COMMAND_UDW); + } + if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) || IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0) || IS_PONTEVECCHIO(i915) || @@ -3027,6 +3007,33 @@ general_render_compute_wa_init(struct intel_engine_cs *engine, struct i915_wa_li wa_masked_en(wal, VFG_PREEMPTION_CHICKEN, POLYGON_TRIFAN_LINELOOP_DISABLE); } + if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_C0) || + IS_DG2_G11(i915)) { + /* + * Wa_22012826095:dg2 + * Wa_22013059131:dg2 + */ + wa_mcr_write_clr_set(wal, LSC_CHICKEN_BIT_0_UDW, + MAXREQS_PER_BANK, + REG_FIELD_PREP(MAXREQS_PER_BANK, 2)); + + /* Wa_22013059131:dg2 */ + wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0, + FORCE_1_SUB_MESSAGE_PER_FRAGMENT); + } + + if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_A0, STEP_B0)) { + /* + * Wa_14010918519:dg2_g10 + * + * LSC_CHICKEN_BIT_0 always reads back as 0 is this stepping, + * so ignoring verification. + */ + wa_mcr_add(wal, LSC_CHICKEN_BIT_0_UDW, 0, + FORCE_SLM_FENCE_SCOPE_TO_TILE | FORCE_UGM_FENCE_SCOPE_TO_TILE, + 0, false); + } + if (IS_PONTEVECCHIO(i915)) { /* Wa_16016694945 */ wa_masked_en(wal, XEHPC_LNCFMISCCFGREG0, XEHPC_OVRLSCCC); -- 2.39.0 ^ permalink raw reply related [flat|nested] 12+ messages in thread
* Re: [Intel-gfx] [PATCH v2 2/2] drm/i915/gt: Move LSC_CHICKEN_BIT* workarounds to correct function 2023-01-18 15:52 ` [Intel-gfx] [PATCH v2 2/2] drm/i915/gt: Move LSC_CHICKEN_BIT* workarounds to correct function Gustavo Sousa @ 2023-01-19 21:57 ` Rodrigo Vivi 2023-01-19 22:24 ` Gustavo Sousa 0 siblings, 1 reply; 12+ messages in thread From: Rodrigo Vivi @ 2023-01-19 21:57 UTC (permalink / raw) To: Gustavo Sousa; +Cc: intel-gfx On Wed, Jan 18, 2023 at 12:52:49PM -0300, Gustavo Sousa wrote: > That register doesn't belong to a specific engine, so the proper > placement for workarounds programming it should be > general_render_compute_wa_init(). > > Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> > --- > drivers/gpu/drm/i915/gt/intel_workarounds.c | 65 ++++++++++++--------- > 1 file changed, 36 insertions(+), 29 deletions(-) > > diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c > index ef6065ce8267..918a271447e2 100644 > --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c > +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c > @@ -2341,10 +2341,6 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) > /* Wa_1509727124 */ > wa_mcr_masked_en(wal, GEN10_SAMPLER_MODE, > SC_DISABLE_POWER_OPTIMIZATION_EBB); > - > - /* Wa_22013037850 */ > - wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0_UDW, > - DISABLE_128B_EVICTION_COMMAND_UDW); > } > > if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_FOREVER) || > @@ -2373,21 +2369,6 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) > GEN12_DISABLE_HDR_PAST_PAYLOAD_HOLD_FIX); > } > > - if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_C0) || > - IS_DG2_G11(i915)) { > - /* > - * Wa_22012826095:dg2 > - * Wa_22013059131:dg2 > - */ > - wa_mcr_write_clr_set(wal, LSC_CHICKEN_BIT_0_UDW, > - MAXREQS_PER_BANK, > - REG_FIELD_PREP(MAXREQS_PER_BANK, 2)); > - > - /* Wa_22013059131:dg2 */ > - wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0, > - FORCE_1_SUB_MESSAGE_PER_FRAGMENT); > - } > - > /* Wa_1308578152:dg2_g10 when first gslice is fused off */ > if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_C0) && > needs_wa_1308578152(engine)) { > @@ -2412,16 +2393,6 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) > */ > wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN, > MDQ_ARBITRATION_MODE | UGM_BACKUP_MODE); > - > - /* > - * Wa_14010918519:dg2_g10 > - * > - * LSC_CHICKEN_BIT_0 always reads back as 0 is this stepping, > - * so ignoring verification. > - */ > - wa_mcr_add(wal, LSC_CHICKEN_BIT_0_UDW, 0, > - FORCE_SLM_FENCE_SCOPE_TO_TILE | FORCE_UGM_FENCE_SCOPE_TO_TILE, > - 0, false); > } > > if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_A0, STEP_B0)) { > @@ -3006,6 +2977,15 @@ general_render_compute_wa_init(struct intel_engine_cs *engine, struct i915_wa_li > > add_render_compute_tuning_settings(i915, wal); > > + if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) || > + IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0) || > + IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_FOREVER) || > + IS_DG2_G11(i915) || IS_DG2_G12(i915)) { > + /* Wa_22013037850 */ > + wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0_UDW, > + DISABLE_128B_EVICTION_COMMAND_UDW); > + } > + > if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) || > IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0) || > IS_PONTEVECCHIO(i915) || > @@ -3027,6 +3007,33 @@ general_render_compute_wa_init(struct intel_engine_cs *engine, struct i915_wa_li > wa_masked_en(wal, VFG_PREEMPTION_CHICKEN, POLYGON_TRIFAN_LINELOOP_DISABLE); > } > > + if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_C0) || > + IS_DG2_G11(i915)) { > + /* > + * Wa_22012826095:dg2 > + * Wa_22013059131:dg2 > + */ > + wa_mcr_write_clr_set(wal, LSC_CHICKEN_BIT_0_UDW, > + MAXREQS_PER_BANK, > + REG_FIELD_PREP(MAXREQS_PER_BANK, 2)); > + > + /* Wa_22013059131:dg2 */ > + wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0, > + FORCE_1_SUB_MESSAGE_PER_FRAGMENT); > + } > + > + if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_A0, STEP_B0)) { > + /* > + * Wa_14010918519:dg2_g10 > + * > + * LSC_CHICKEN_BIT_0 always reads back as 0 is this stepping, > + * so ignoring verification. > + */ > + wa_mcr_add(wal, LSC_CHICKEN_BIT_0_UDW, 0, > + FORCE_SLM_FENCE_SCOPE_TO_TILE | FORCE_UGM_FENCE_SCOPE_TO_TILE, > + 0, false); > + } > + > if (IS_PONTEVECCHIO(i915)) { > /* Wa_16016694945 */ > wa_masked_en(wal, XEHPC_LNCFMISCCFGREG0, XEHPC_OVRLSCCC); > -- > 2.39.0 > ^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [Intel-gfx] [PATCH v2 2/2] drm/i915/gt: Move LSC_CHICKEN_BIT* workarounds to correct function 2023-01-19 21:57 ` Rodrigo Vivi @ 2023-01-19 22:24 ` Gustavo Sousa 2023-01-19 22:28 ` Vivi, Rodrigo 0 siblings, 1 reply; 12+ messages in thread From: Gustavo Sousa @ 2023-01-19 22:24 UTC (permalink / raw) To: Rodrigo Vivi; +Cc: Lucas De Marchi, intel-gfx On Thu, Jan 19, 2023 at 04:57:09PM -0500, Rodrigo Vivi wrote: > On Wed, Jan 18, 2023 at 12:52:49PM -0300, Gustavo Sousa wrote: > > That register doesn't belong to a specific engine, so the proper > > placement for workarounds programming it should be > > general_render_compute_wa_init(). > > > > Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com> > > Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Thanks for the review, Rodrigo! Last time I talked with the team, Lucas suspected there could be a reason why the workarounds were in their current places. I'll include him and Matt Roper here, since they had assigned themselves to check this. I think we should wait for their input before applying this patch. > > > --- > > drivers/gpu/drm/i915/gt/intel_workarounds.c | 65 ++++++++++++--------- > > 1 file changed, 36 insertions(+), 29 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c > > index ef6065ce8267..918a271447e2 100644 > > --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c > > +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c > > @@ -2341,10 +2341,6 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) > > /* Wa_1509727124 */ > > wa_mcr_masked_en(wal, GEN10_SAMPLER_MODE, > > SC_DISABLE_POWER_OPTIMIZATION_EBB); > > - > > - /* Wa_22013037850 */ > > - wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0_UDW, > > - DISABLE_128B_EVICTION_COMMAND_UDW); > > } > > > > if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_FOREVER) || > > @@ -2373,21 +2369,6 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) > > GEN12_DISABLE_HDR_PAST_PAYLOAD_HOLD_FIX); > > } > > > > - if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_C0) || > > - IS_DG2_G11(i915)) { > > - /* > > - * Wa_22012826095:dg2 > > - * Wa_22013059131:dg2 > > - */ > > - wa_mcr_write_clr_set(wal, LSC_CHICKEN_BIT_0_UDW, > > - MAXREQS_PER_BANK, > > - REG_FIELD_PREP(MAXREQS_PER_BANK, 2)); > > - > > - /* Wa_22013059131:dg2 */ > > - wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0, > > - FORCE_1_SUB_MESSAGE_PER_FRAGMENT); > > - } > > - > > /* Wa_1308578152:dg2_g10 when first gslice is fused off */ > > if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_C0) && > > needs_wa_1308578152(engine)) { > > @@ -2412,16 +2393,6 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) > > */ > > wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN, > > MDQ_ARBITRATION_MODE | UGM_BACKUP_MODE); > > - > > - /* > > - * Wa_14010918519:dg2_g10 > > - * > > - * LSC_CHICKEN_BIT_0 always reads back as 0 is this stepping, > > - * so ignoring verification. > > - */ > > - wa_mcr_add(wal, LSC_CHICKEN_BIT_0_UDW, 0, > > - FORCE_SLM_FENCE_SCOPE_TO_TILE | FORCE_UGM_FENCE_SCOPE_TO_TILE, > > - 0, false); > > } > > > > if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_A0, STEP_B0)) { > > @@ -3006,6 +2977,15 @@ general_render_compute_wa_init(struct intel_engine_cs *engine, struct i915_wa_li > > > > add_render_compute_tuning_settings(i915, wal); > > > > + if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) || > > + IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0) || > > + IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_FOREVER) || > > + IS_DG2_G11(i915) || IS_DG2_G12(i915)) { > > + /* Wa_22013037850 */ > > + wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0_UDW, > > + DISABLE_128B_EVICTION_COMMAND_UDW); > > + } > > + > > if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) || > > IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0) || > > IS_PONTEVECCHIO(i915) || > > @@ -3027,6 +3007,33 @@ general_render_compute_wa_init(struct intel_engine_cs *engine, struct i915_wa_li > > wa_masked_en(wal, VFG_PREEMPTION_CHICKEN, POLYGON_TRIFAN_LINELOOP_DISABLE); > > } > > > > + if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_C0) || > > + IS_DG2_G11(i915)) { > > + /* > > + * Wa_22012826095:dg2 > > + * Wa_22013059131:dg2 > > + */ > > + wa_mcr_write_clr_set(wal, LSC_CHICKEN_BIT_0_UDW, > > + MAXREQS_PER_BANK, > > + REG_FIELD_PREP(MAXREQS_PER_BANK, 2)); > > + > > + /* Wa_22013059131:dg2 */ > > + wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0, > > + FORCE_1_SUB_MESSAGE_PER_FRAGMENT); > > + } > > + > > + if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_A0, STEP_B0)) { > > + /* > > + * Wa_14010918519:dg2_g10 > > + * > > + * LSC_CHICKEN_BIT_0 always reads back as 0 is this stepping, > > + * so ignoring verification. > > + */ > > + wa_mcr_add(wal, LSC_CHICKEN_BIT_0_UDW, 0, > > + FORCE_SLM_FENCE_SCOPE_TO_TILE | FORCE_UGM_FENCE_SCOPE_TO_TILE, > > + 0, false); > > + } > > + > > if (IS_PONTEVECCHIO(i915)) { > > /* Wa_16016694945 */ > > wa_masked_en(wal, XEHPC_LNCFMISCCFGREG0, XEHPC_OVRLSCCC); > > -- > > 2.39.0 > > ^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [Intel-gfx] [PATCH v2 2/2] drm/i915/gt: Move LSC_CHICKEN_BIT* workarounds to correct function 2023-01-19 22:24 ` Gustavo Sousa @ 2023-01-19 22:28 ` Vivi, Rodrigo 2023-01-19 23:03 ` Matt Roper 0 siblings, 1 reply; 12+ messages in thread From: Vivi, Rodrigo @ 2023-01-19 22:28 UTC (permalink / raw) To: Sousa, Gustavo; +Cc: De Marchi, Lucas, intel-gfx@lists.freedesktop.org On Thu, 2023-01-19 at 19:24 -0300, Gustavo Sousa wrote: > On Thu, Jan 19, 2023 at 04:57:09PM -0500, Rodrigo Vivi wrote: > > On Wed, Jan 18, 2023 at 12:52:49PM -0300, Gustavo Sousa wrote: > > > That register doesn't belong to a specific engine, so the proper > > > placement for workarounds programming it should be > > > general_render_compute_wa_init(). > > > > > > Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com> > > > > Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> > > Thanks for the review, Rodrigo! > > Last time I talked with the team, Lucas suspected there could be a > reason why > the workarounds were in their current places. I'll include him and > Matt Roper > here, since they had assigned themselves to check this. > > I think we should wait for their input before applying this patch. ops, I have just pushed them... > > > > > > --- > > > drivers/gpu/drm/i915/gt/intel_workarounds.c | 65 ++++++++++++--- > > > ------ > > > 1 file changed, 36 insertions(+), 29 deletions(-) > > > > > > diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c > > > b/drivers/gpu/drm/i915/gt/intel_workarounds.c > > > index ef6065ce8267..918a271447e2 100644 > > > --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c > > > +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c > > > @@ -2341,10 +2341,6 @@ rcs_engine_wa_init(struct intel_engine_cs > > > *engine, struct i915_wa_list *wal) > > > /* Wa_1509727124 */ > > > wa_mcr_masked_en(wal, GEN10_SAMPLER_MODE, > > > > > > SC_DISABLE_POWER_OPTIMIZATION_EBB); > > > - > > > - /* Wa_22013037850 */ > > > - wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0_UDW, > > > - > > > DISABLE_128B_EVICTION_COMMAND_UDW); > > > } > > > > > > if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, > > > STEP_FOREVER) || > > > @@ -2373,21 +2369,6 @@ rcs_engine_wa_init(struct intel_engine_cs > > > *engine, struct i915_wa_list *wal) > > > > > > GEN12_DISABLE_HDR_PAST_PAYLOAD_HOLD_FIX); > > > } > > > > > > - if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_C0) || > > > - IS_DG2_G11(i915)) { > > > - /* > > > - * Wa_22012826095:dg2 > > > - * Wa_22013059131:dg2 > > > - */ > > > - wa_mcr_write_clr_set(wal, LSC_CHICKEN_BIT_0_UDW, > > > - MAXREQS_PER_BANK, > > > - > > > REG_FIELD_PREP(MAXREQS_PER_BANK, 2)); > > > - > > > - /* Wa_22013059131:dg2 */ > > > - wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0, > > > - > > > FORCE_1_SUB_MESSAGE_PER_FRAGMENT); > > > - } > > > - > > > /* Wa_1308578152:dg2_g10 when first gslice is fused off > > > */ > > > if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_C0) && > > > needs_wa_1308578152(engine)) { > > > @@ -2412,16 +2393,6 @@ rcs_engine_wa_init(struct intel_engine_cs > > > *engine, struct i915_wa_list *wal) > > > */ > > > wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN, > > > MDQ_ARBITRATION_MODE | > > > UGM_BACKUP_MODE); > > > - > > > - /* > > > - * Wa_14010918519:dg2_g10 > > > - * > > > - * LSC_CHICKEN_BIT_0 always reads back as 0 is > > > this stepping, > > > - * so ignoring verification. > > > - */ > > > - wa_mcr_add(wal, LSC_CHICKEN_BIT_0_UDW, 0, > > > - FORCE_SLM_FENCE_SCOPE_TO_TILE | > > > FORCE_UGM_FENCE_SCOPE_TO_TILE, > > > - 0, false); > > > } > > > > > > if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_A0, STEP_B0)) { > > > @@ -3006,6 +2977,15 @@ general_render_compute_wa_init(struct > > > intel_engine_cs *engine, struct i915_wa_li > > > > > > add_render_compute_tuning_settings(i915, wal); > > > > > > + if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) || > > > + IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0) || > > > + IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, > > > STEP_FOREVER) || > > > + IS_DG2_G11(i915) || IS_DG2_G12(i915)) { > > > + /* Wa_22013037850 */ > > > + wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0_UDW, > > > + DISABLE_128B_EVICTION_COMMAND_UDW > > > ); > > > + } > > > + > > > if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) || > > > IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0) || > > > IS_PONTEVECCHIO(i915) || > > > @@ -3027,6 +3007,33 @@ general_render_compute_wa_init(struct > > > intel_engine_cs *engine, struct i915_wa_li > > > wa_masked_en(wal, VFG_PREEMPTION_CHICKEN, > > > POLYGON_TRIFAN_LINELOOP_DISABLE); > > > } > > > > > > + if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_C0) || > > > + IS_DG2_G11(i915)) { > > > + /* > > > + * Wa_22012826095:dg2 > > > + * Wa_22013059131:dg2 > > > + */ > > > + wa_mcr_write_clr_set(wal, LSC_CHICKEN_BIT_0_UDW, > > > + MAXREQS_PER_BANK, > > > + > > > REG_FIELD_PREP(MAXREQS_PER_BANK, 2)); > > > + > > > + /* Wa_22013059131:dg2 */ > > > + wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0, > > > + FORCE_1_SUB_MESSAGE_PER_FRAGMENT) > > > ; > > > + } > > > + > > > + if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_A0, STEP_B0)) { > > > + /* > > > + * Wa_14010918519:dg2_g10 > > > + * > > > + * LSC_CHICKEN_BIT_0 always reads back as 0 is > > > this stepping, > > > + * so ignoring verification. > > > + */ > > > + wa_mcr_add(wal, LSC_CHICKEN_BIT_0_UDW, 0, > > > + FORCE_SLM_FENCE_SCOPE_TO_TILE | > > > FORCE_UGM_FENCE_SCOPE_TO_TILE, > > > + 0, false); > > > + } > > > + > > > if (IS_PONTEVECCHIO(i915)) { > > > /* Wa_16016694945 */ > > > wa_masked_en(wal, XEHPC_LNCFMISCCFGREG0, > > > XEHPC_OVRLSCCC); > > > -- > > > 2.39.0 > > > ^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [Intel-gfx] [PATCH v2 2/2] drm/i915/gt: Move LSC_CHICKEN_BIT* workarounds to correct function 2023-01-19 22:28 ` Vivi, Rodrigo @ 2023-01-19 23:03 ` Matt Roper 2023-01-20 22:46 ` Lucas De Marchi 0 siblings, 1 reply; 12+ messages in thread From: Matt Roper @ 2023-01-19 23:03 UTC (permalink / raw) To: Vivi, Rodrigo; +Cc: intel-gfx@lists.freedesktop.org, De Marchi, Lucas On Thu, Jan 19, 2023 at 02:28:13PM -0800, Vivi, Rodrigo wrote: > On Thu, 2023-01-19 at 19:24 -0300, Gustavo Sousa wrote: > > On Thu, Jan 19, 2023 at 04:57:09PM -0500, Rodrigo Vivi wrote: > > > On Wed, Jan 18, 2023 at 12:52:49PM -0300, Gustavo Sousa wrote: > > > > That register doesn't belong to a specific engine, so the proper > > > > placement for workarounds programming it should be > > > > general_render_compute_wa_init(). > > > > > > > > Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com> > > > > > > Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> > > > > Thanks for the review, Rodrigo! > > > > Last time I talked with the team, Lucas suspected there could be a > > reason why > > the workarounds were in their current places. I'll include him and > > Matt Roper > > here, since they had assigned themselves to check this. > > > > I think we should wait for their input before applying this patch. > > ops, I have just pushed them... I didn't review each workaround in detail, but at a high level the patch below looks correct to me. The intention was always to go back and find all the workarounds touching non-RCS, non-CCS registers that are part of the shared render/compute domain and move them to this general_render_compute_wa_init() function. The effort just stalled out because the developer working on it left and nobody else has had time to pick it up yet; it's been on our todo list for a while. Moving these workarounds from rcs_engine_wa_init() to general_render_compute_wa_init() would become very important if a SKU of these platforms ever shows up with a fused-off render engine. In that case the workarounds would get missed (due to lack of RCS), which would negatively impact the behavior of the remaining CCS engines. However that's just a theoretical problem today; in practice all DG2 and MTL platforms have an RCS engine, so the code movement below will not cause any functional change. But it's still good to have Gustavo finally cleaning this up because we never know what the future holds. Matt > > > > > > > > > > --- > > > > drivers/gpu/drm/i915/gt/intel_workarounds.c | 65 ++++++++++++--- > > > > ------ > > > > 1 file changed, 36 insertions(+), 29 deletions(-) > > > > > > > > diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c > > > > b/drivers/gpu/drm/i915/gt/intel_workarounds.c > > > > index ef6065ce8267..918a271447e2 100644 > > > > --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c > > > > +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c > > > > @@ -2341,10 +2341,6 @@ rcs_engine_wa_init(struct intel_engine_cs > > > > *engine, struct i915_wa_list *wal) > > > > /* Wa_1509727124 */ > > > > wa_mcr_masked_en(wal, GEN10_SAMPLER_MODE, > > > > > > > > SC_DISABLE_POWER_OPTIMIZATION_EBB); > > > > - > > > > - /* Wa_22013037850 */ > > > > - wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0_UDW, > > > > - > > > > DISABLE_128B_EVICTION_COMMAND_UDW); > > > > } > > > > > > > > if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, > > > > STEP_FOREVER) || > > > > @@ -2373,21 +2369,6 @@ rcs_engine_wa_init(struct intel_engine_cs > > > > *engine, struct i915_wa_list *wal) > > > > > > > > GEN12_DISABLE_HDR_PAST_PAYLOAD_HOLD_FIX); > > > > } > > > > > > > > - if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_C0) || > > > > - IS_DG2_G11(i915)) { > > > > - /* > > > > - * Wa_22012826095:dg2 > > > > - * Wa_22013059131:dg2 > > > > - */ > > > > - wa_mcr_write_clr_set(wal, LSC_CHICKEN_BIT_0_UDW, > > > > - MAXREQS_PER_BANK, > > > > - > > > > REG_FIELD_PREP(MAXREQS_PER_BANK, 2)); > > > > - > > > > - /* Wa_22013059131:dg2 */ > > > > - wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0, > > > > - > > > > FORCE_1_SUB_MESSAGE_PER_FRAGMENT); > > > > - } > > > > - > > > > /* Wa_1308578152:dg2_g10 when first gslice is fused off > > > > */ > > > > if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_C0) && > > > > needs_wa_1308578152(engine)) { > > > > @@ -2412,16 +2393,6 @@ rcs_engine_wa_init(struct intel_engine_cs > > > > *engine, struct i915_wa_list *wal) > > > > */ > > > > wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN, > > > > MDQ_ARBITRATION_MODE | > > > > UGM_BACKUP_MODE); > > > > - > > > > - /* > > > > - * Wa_14010918519:dg2_g10 > > > > - * > > > > - * LSC_CHICKEN_BIT_0 always reads back as 0 is > > > > this stepping, > > > > - * so ignoring verification. > > > > - */ > > > > - wa_mcr_add(wal, LSC_CHICKEN_BIT_0_UDW, 0, > > > > - FORCE_SLM_FENCE_SCOPE_TO_TILE | > > > > FORCE_UGM_FENCE_SCOPE_TO_TILE, > > > > - 0, false); > > > > } > > > > > > > > if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_A0, STEP_B0)) { > > > > @@ -3006,6 +2977,15 @@ general_render_compute_wa_init(struct > > > > intel_engine_cs *engine, struct i915_wa_li > > > > > > > > add_render_compute_tuning_settings(i915, wal); > > > > > > > > + if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) || > > > > + IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0) || > > > > + IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, > > > > STEP_FOREVER) || > > > > + IS_DG2_G11(i915) || IS_DG2_G12(i915)) { > > > > + /* Wa_22013037850 */ > > > > + wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0_UDW, > > > > + DISABLE_128B_EVICTION_COMMAND_UDW > > > > ); > > > > + } > > > > + > > > > if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) || > > > > IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0) || > > > > IS_PONTEVECCHIO(i915) || > > > > @@ -3027,6 +3007,33 @@ general_render_compute_wa_init(struct > > > > intel_engine_cs *engine, struct i915_wa_li > > > > wa_masked_en(wal, VFG_PREEMPTION_CHICKEN, > > > > POLYGON_TRIFAN_LINELOOP_DISABLE); > > > > } > > > > > > > > + if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_C0) || > > > > + IS_DG2_G11(i915)) { > > > > + /* > > > > + * Wa_22012826095:dg2 > > > > + * Wa_22013059131:dg2 > > > > + */ > > > > + wa_mcr_write_clr_set(wal, LSC_CHICKEN_BIT_0_UDW, > > > > + MAXREQS_PER_BANK, > > > > + > > > > REG_FIELD_PREP(MAXREQS_PER_BANK, 2)); > > > > + > > > > + /* Wa_22013059131:dg2 */ > > > > + wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0, > > > > + FORCE_1_SUB_MESSAGE_PER_FRAGMENT) > > > > ; > > > > + } > > > > + > > > > + if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_A0, STEP_B0)) { > > > > + /* > > > > + * Wa_14010918519:dg2_g10 > > > > + * > > > > + * LSC_CHICKEN_BIT_0 always reads back as 0 is > > > > this stepping, > > > > + * so ignoring verification. > > > > + */ > > > > + wa_mcr_add(wal, LSC_CHICKEN_BIT_0_UDW, 0, > > > > + FORCE_SLM_FENCE_SCOPE_TO_TILE | > > > > FORCE_UGM_FENCE_SCOPE_TO_TILE, > > > > + 0, false); > > > > + } > > > > + > > > > if (IS_PONTEVECCHIO(i915)) { > > > > /* Wa_16016694945 */ > > > > wa_masked_en(wal, XEHPC_LNCFMISCCFGREG0, > > > > XEHPC_OVRLSCCC); > > > > -- > > > > 2.39.0 > > > > > -- Matt Roper Graphics Software Engineer Linux GPU Platform Enablement Intel Corporation ^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [Intel-gfx] [PATCH v2 2/2] drm/i915/gt: Move LSC_CHICKEN_BIT* workarounds to correct function 2023-01-19 23:03 ` Matt Roper @ 2023-01-20 22:46 ` Lucas De Marchi 0 siblings, 0 replies; 12+ messages in thread From: Lucas De Marchi @ 2023-01-20 22:46 UTC (permalink / raw) To: Matt Roper; +Cc: intel-gfx@lists.freedesktop.org, Vivi, Rodrigo On Thu, Jan 19, 2023 at 03:03:30PM -0800, Matt Roper wrote: >On Thu, Jan 19, 2023 at 02:28:13PM -0800, Vivi, Rodrigo wrote: >> On Thu, 2023-01-19 at 19:24 -0300, Gustavo Sousa wrote: >> > On Thu, Jan 19, 2023 at 04:57:09PM -0500, Rodrigo Vivi wrote: >> > > On Wed, Jan 18, 2023 at 12:52:49PM -0300, Gustavo Sousa wrote: >> > > > That register doesn't belong to a specific engine, so the proper >> > > > placement for workarounds programming it should be >> > > > general_render_compute_wa_init(). >> > > > >> > > > Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com> >> > > >> > > Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> >> > >> > Thanks for the review, Rodrigo! >> > >> > Last time I talked with the team, Lucas suspected there could be a >> > reason why >> > the workarounds were in their current places. I'll include him and >> > Matt Roper >> > here, since they had assigned themselves to check this. >> > >> > I think we should wait for their input before applying this patch. >> >> ops, I have just pushed them... > >I didn't review each workaround in detail, but at a high level the patch >below looks correct to me. The intention was always to go back and find >all the workarounds touching non-RCS, non-CCS registers that are part of >the shared render/compute domain and move them to this >general_render_compute_wa_init() function. The effort just stalled out >because the developer working on it left and nobody else has had time to >pick it up yet; it's been on our todo list for a while. > >Moving these workarounds from rcs_engine_wa_init() to >general_render_compute_wa_init() would become very important if a SKU of >these platforms ever shows up with a fused-off render engine. In that >case the workarounds would get missed (due to lack of RCS), which would >negatively impact the behavior of the remaining CCS engines. However >that's just a theoretical problem today; in practice all DG2 and MTL >platforms have an RCS engine, so the code movement below will not cause >any functional change. But it's still good to have Gustavo finally >cleaning this up because we never know what the future holds. it may be that my fuzzy memory about this is that we didn't have yet the general_render_compute_* function to add this kind of WA to, so some of the workarounds got added to the engine because these registers reset when either compute or render reset. So, yes... I agree this should be fine. Lucas De Marchi > > >Matt > >> >> > >> > > >> > > > --- >> > > > drivers/gpu/drm/i915/gt/intel_workarounds.c | 65 ++++++++++++--- >> > > > ------ >> > > > 1 file changed, 36 insertions(+), 29 deletions(-) >> > > > >> > > > diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c >> > > > b/drivers/gpu/drm/i915/gt/intel_workarounds.c >> > > > index ef6065ce8267..918a271447e2 100644 >> > > > --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c >> > > > +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c >> > > > @@ -2341,10 +2341,6 @@ rcs_engine_wa_init(struct intel_engine_cs >> > > > *engine, struct i915_wa_list *wal) >> > > > /* Wa_1509727124 */ >> > > > wa_mcr_masked_en(wal, GEN10_SAMPLER_MODE, >> > > > >> > > > SC_DISABLE_POWER_OPTIMIZATION_EBB); >> > > > - >> > > > - /* Wa_22013037850 */ >> > > > - wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0_UDW, >> > > > - >> > > > DISABLE_128B_EVICTION_COMMAND_UDW); >> > > > } >> > > > >> > > > if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, >> > > > STEP_FOREVER) || >> > > > @@ -2373,21 +2369,6 @@ rcs_engine_wa_init(struct intel_engine_cs >> > > > *engine, struct i915_wa_list *wal) >> > > > >> > > > GEN12_DISABLE_HDR_PAST_PAYLOAD_HOLD_FIX); >> > > > } >> > > > >> > > > - if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_C0) || >> > > > - IS_DG2_G11(i915)) { >> > > > - /* >> > > > - * Wa_22012826095:dg2 >> > > > - * Wa_22013059131:dg2 >> > > > - */ >> > > > - wa_mcr_write_clr_set(wal, LSC_CHICKEN_BIT_0_UDW, >> > > > - MAXREQS_PER_BANK, >> > > > - >> > > > REG_FIELD_PREP(MAXREQS_PER_BANK, 2)); >> > > > - >> > > > - /* Wa_22013059131:dg2 */ >> > > > - wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0, >> > > > - >> > > > FORCE_1_SUB_MESSAGE_PER_FRAGMENT); >> > > > - } >> > > > - >> > > > /* Wa_1308578152:dg2_g10 when first gslice is fused off >> > > > */ >> > > > if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_C0) && >> > > > needs_wa_1308578152(engine)) { >> > > > @@ -2412,16 +2393,6 @@ rcs_engine_wa_init(struct intel_engine_cs >> > > > *engine, struct i915_wa_list *wal) >> > > > */ >> > > > wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN, >> > > > MDQ_ARBITRATION_MODE | >> > > > UGM_BACKUP_MODE); >> > > > - >> > > > - /* >> > > > - * Wa_14010918519:dg2_g10 >> > > > - * >> > > > - * LSC_CHICKEN_BIT_0 always reads back as 0 is >> > > > this stepping, >> > > > - * so ignoring verification. >> > > > - */ >> > > > - wa_mcr_add(wal, LSC_CHICKEN_BIT_0_UDW, 0, >> > > > - FORCE_SLM_FENCE_SCOPE_TO_TILE | >> > > > FORCE_UGM_FENCE_SCOPE_TO_TILE, >> > > > - 0, false); >> > > > } >> > > > >> > > > if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_A0, STEP_B0)) { >> > > > @@ -3006,6 +2977,15 @@ general_render_compute_wa_init(struct >> > > > intel_engine_cs *engine, struct i915_wa_li >> > > > >> > > > add_render_compute_tuning_settings(i915, wal); >> > > > >> > > > + if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) || >> > > > + IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0) || >> > > > + IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, >> > > > STEP_FOREVER) || >> > > > + IS_DG2_G11(i915) || IS_DG2_G12(i915)) { >> > > > + /* Wa_22013037850 */ >> > > > + wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0_UDW, >> > > > + DISABLE_128B_EVICTION_COMMAND_UDW >> > > > ); >> > > > + } >> > > > + >> > > > if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) || >> > > > IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0) || >> > > > IS_PONTEVECCHIO(i915) || >> > > > @@ -3027,6 +3007,33 @@ general_render_compute_wa_init(struct >> > > > intel_engine_cs *engine, struct i915_wa_li >> > > > wa_masked_en(wal, VFG_PREEMPTION_CHICKEN, >> > > > POLYGON_TRIFAN_LINELOOP_DISABLE); >> > > > } >> > > > >> > > > + if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_C0) || >> > > > + IS_DG2_G11(i915)) { >> > > > + /* >> > > > + * Wa_22012826095:dg2 >> > > > + * Wa_22013059131:dg2 >> > > > + */ >> > > > + wa_mcr_write_clr_set(wal, LSC_CHICKEN_BIT_0_UDW, >> > > > + MAXREQS_PER_BANK, >> > > > + >> > > > REG_FIELD_PREP(MAXREQS_PER_BANK, 2)); >> > > > + >> > > > + /* Wa_22013059131:dg2 */ >> > > > + wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0, >> > > > + FORCE_1_SUB_MESSAGE_PER_FRAGMENT) >> > > > ; >> > > > + } >> > > > + >> > > > + if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_A0, STEP_B0)) { >> > > > + /* >> > > > + * Wa_14010918519:dg2_g10 >> > > > + * >> > > > + * LSC_CHICKEN_BIT_0 always reads back as 0 is >> > > > this stepping, >> > > > + * so ignoring verification. >> > > > + */ >> > > > + wa_mcr_add(wal, LSC_CHICKEN_BIT_0_UDW, 0, >> > > > + FORCE_SLM_FENCE_SCOPE_TO_TILE | >> > > > FORCE_UGM_FENCE_SCOPE_TO_TILE, >> > > > + 0, false); >> > > > + } >> > > > + >> > > > if (IS_PONTEVECCHIO(i915)) { >> > > > /* Wa_16016694945 */ >> > > > wa_masked_en(wal, XEHPC_LNCFMISCCFGREG0, >> > > > XEHPC_OVRLSCCC); >> > > > -- >> > > > 2.39.0 >> > > > >> > >-- >Matt Roper >Graphics Software Engineer >Linux GPU Platform Enablement >Intel Corporation ^ permalink raw reply [flat|nested] 12+ messages in thread
* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/gt: Move LSC_CHICKEN_BIT* workarounds to correct function (Series) 2023-01-18 15:52 [Intel-gfx] [PATCH v2 0/2] drm/i915/gt: Move LSC_CHICKEN_BIT* workarounds to correct function (Series) Gustavo Sousa 2023-01-18 15:52 ` [Intel-gfx] [PATCH v2 1/2] drm/i915/doc: Document where to implement register workarounds Gustavo Sousa 2023-01-18 15:52 ` [Intel-gfx] [PATCH v2 2/2] drm/i915/gt: Move LSC_CHICKEN_BIT* workarounds to correct function Gustavo Sousa @ 2023-01-18 23:42 ` Patchwork 2023-01-18 23:57 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork 2023-01-19 22:02 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork 4 siblings, 0 replies; 12+ messages in thread From: Patchwork @ 2023-01-18 23:42 UTC (permalink / raw) To: Gustavo Sousa; +Cc: intel-gfx == Series Details == Series: drm/i915/gt: Move LSC_CHICKEN_BIT* workarounds to correct function (Series) URL : https://patchwork.freedesktop.org/series/113036/ State : warning == Summary == Error: dim checkpatch failed 6c2b52a5e74a drm/i915/doc: Document where to implement register workarounds -:35: WARNING:REPEATED_WORD: Possible repeated word: 'of' #35: FILE: drivers/gpu/drm/i915/gt/intel_workarounds.c:52: + * engine's MMIO range but that are part of of the common RCS/CCS reset domain total: 0 errors, 1 warnings, 0 checks, 37 lines checked 1deb862b66a9 drm/i915/gt: Move LSC_CHICKEN_BIT* workarounds to correct function ^ permalink raw reply [flat|nested] 12+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/gt: Move LSC_CHICKEN_BIT* workarounds to correct function (Series) 2023-01-18 15:52 [Intel-gfx] [PATCH v2 0/2] drm/i915/gt: Move LSC_CHICKEN_BIT* workarounds to correct function (Series) Gustavo Sousa ` (2 preceding siblings ...) 2023-01-18 23:42 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/gt: Move LSC_CHICKEN_BIT* workarounds to correct function (Series) Patchwork @ 2023-01-18 23:57 ` Patchwork 2023-01-19 22:02 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork 4 siblings, 0 replies; 12+ messages in thread From: Patchwork @ 2023-01-18 23:57 UTC (permalink / raw) To: Gustavo Sousa; +Cc: intel-gfx [-- Attachment #1: Type: text/plain, Size: 4724 bytes --] == Series Details == Series: drm/i915/gt: Move LSC_CHICKEN_BIT* workarounds to correct function (Series) URL : https://patchwork.freedesktop.org/series/113036/ State : success == Summary == CI Bug Log - changes from CI_DRM_12605 -> Patchwork_113036v1 ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113036v1/index.html Participating hosts (43 -> 41) ------------------------------ Missing (2): fi-bsw-kefka fi-snb-2520m Known issues ------------ Here are the changes found in Patchwork_113036v1 that come from known issues: ### IGT changes ### #### Issues hit #### * igt@gem_exec_gttfill@basic: - fi-pnv-d510: [PASS][1] -> [FAIL][2] ([i915#7229]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12605/fi-pnv-d510/igt@gem_exec_gttfill@basic.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113036v1/fi-pnv-d510/igt@gem_exec_gttfill@basic.html * igt@i915_selftest@live@hangcheck: - bat-dg1-6: [PASS][3] -> [INCOMPLETE][4] ([i915#4983]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12605/bat-dg1-6/igt@i915_selftest@live@hangcheck.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113036v1/bat-dg1-6/igt@i915_selftest@live@hangcheck.html * igt@kms_chamelium_hpd@common-hpd-after-suspend: - fi-rkl-guc: NOTRUN -> [SKIP][5] ([i915#7828]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113036v1/fi-rkl-guc/igt@kms_chamelium_hpd@common-hpd-after-suspend.html * igt@runner@aborted: - bat-dg1-6: NOTRUN -> [FAIL][6] ([i915#4312]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113036v1/bat-dg1-6/igt@runner@aborted.html #### Possible fixes #### * igt@i915_selftest@live@gt_heartbeat: - fi-apl-guc: [DMESG-FAIL][7] ([i915#5334]) -> [PASS][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12605/fi-apl-guc/igt@i915_selftest@live@gt_heartbeat.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113036v1/fi-apl-guc/igt@i915_selftest@live@gt_heartbeat.html * igt@i915_selftest@live@hangcheck: - fi-rkl-guc: [INCOMPLETE][9] ([i915#4983]) -> [PASS][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12605/fi-rkl-guc/igt@i915_selftest@live@hangcheck.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113036v1/fi-rkl-guc/igt@i915_selftest@live@hangcheck.html * igt@kms_cursor_legacy@basic-busy-flip-before-cursor@atomic-transitions-varying-size: - fi-bsw-n3050: [FAIL][11] ([i915#6298]) -> [PASS][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12605/fi-bsw-n3050/igt@kms_cursor_legacy@basic-busy-flip-before-cursor@atomic-transitions-varying-size.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113036v1/fi-bsw-n3050/igt@kms_cursor_legacy@basic-busy-flip-before-cursor@atomic-transitions-varying-size.html * igt@kms_pipe_crc_basic@suspend-read-crc@pipe-c-hdmi-a-3: - {bat-dg2-11}: [INCOMPLETE][13] -> [PASS][14] [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12605/bat-dg2-11/igt@kms_pipe_crc_basic@suspend-read-crc@pipe-c-hdmi-a-3.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113036v1/bat-dg2-11/igt@kms_pipe_crc_basic@suspend-read-crc@pipe-c-hdmi-a-3.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312 [i915#4983]: https://gitlab.freedesktop.org/drm/intel/issues/4983 [i915#5334]: https://gitlab.freedesktop.org/drm/intel/issues/5334 [i915#6257]: https://gitlab.freedesktop.org/drm/intel/issues/6257 [i915#6298]: https://gitlab.freedesktop.org/drm/intel/issues/6298 [i915#7229]: https://gitlab.freedesktop.org/drm/intel/issues/7229 [i915#7828]: https://gitlab.freedesktop.org/drm/intel/issues/7828 Build changes ------------- * Linux: CI_DRM_12605 -> Patchwork_113036v1 CI-20190529: 20190529 CI_DRM_12605: 1e863b59056127f55822b29a8f0cabf476806979 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_7123: 2b29e8ac07fbcfadc48b9d60e4d736a6e3b289ab @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git Patchwork_113036v1: 1e863b59056127f55822b29a8f0cabf476806979 @ git://anongit.freedesktop.org/gfx-ci/linux ### Linux commits c4868818a79f drm/i915/gt: Move LSC_CHICKEN_BIT* workarounds to correct function f4f0d441b636 drm/i915/doc: Document where to implement register workarounds == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113036v1/index.html [-- Attachment #2: Type: text/html, Size: 5544 bytes --] ^ permalink raw reply [flat|nested] 12+ messages in thread
* [Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/gt: Move LSC_CHICKEN_BIT* workarounds to correct function (Series) 2023-01-18 15:52 [Intel-gfx] [PATCH v2 0/2] drm/i915/gt: Move LSC_CHICKEN_BIT* workarounds to correct function (Series) Gustavo Sousa ` (3 preceding siblings ...) 2023-01-18 23:57 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork @ 2023-01-19 22:02 ` Patchwork 4 siblings, 0 replies; 12+ messages in thread From: Patchwork @ 2023-01-19 22:02 UTC (permalink / raw) To: Gustavo Sousa; +Cc: intel-gfx [-- Attachment #1: Type: text/plain, Size: 18341 bytes --] == Series Details == Series: drm/i915/gt: Move LSC_CHICKEN_BIT* workarounds to correct function (Series) URL : https://patchwork.freedesktop.org/series/113036/ State : success == Summary == CI Bug Log - changes from CI_DRM_12605_full -> Patchwork_113036v1_full ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113036v1/index.html Participating hosts (12 -> 10) ------------------------------ Missing (2): pig-skl-6260u pig-kbl-iris Known issues ------------ Here are the changes found in Patchwork_113036v1_full that come from known issues: ### IGT changes ### #### Issues hit #### * igt@gem_exec_fair@basic-none@vecs0: - shard-glk: [PASS][1] -> [FAIL][2] ([i915#2842]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12605/shard-glk8/igt@gem_exec_fair@basic-none@vecs0.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113036v1/shard-glk6/igt@gem_exec_fair@basic-none@vecs0.html * igt@kms_flip@flip-vs-expired-vblank-interruptible@b-hdmi-a1: - shard-glk: [PASS][3] -> [FAIL][4] ([i915#79]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12605/shard-glk5/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-hdmi-a1.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113036v1/shard-glk8/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-hdmi-a1.html #### Possible fixes #### * igt@gem_eio@in-flight-suspend: - {shard-rkl}: [FAIL][5] ([fdo#103375]) -> [PASS][6] +1 similar issue [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12605/shard-rkl-4/igt@gem_eio@in-flight-suspend.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113036v1/shard-rkl-6/igt@gem_eio@in-flight-suspend.html * igt@gem_exec_fair@basic-pace-share@rcs0: - shard-glk: [FAIL][7] ([i915#2842]) -> [PASS][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12605/shard-glk8/igt@gem_exec_fair@basic-pace-share@rcs0.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113036v1/shard-glk6/igt@gem_exec_fair@basic-pace-share@rcs0.html * igt@gem_exec_fair@basic-pace@rcs0: - {shard-rkl}: [FAIL][9] ([i915#2842]) -> [PASS][10] +2 similar issues [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12605/shard-rkl-6/igt@gem_exec_fair@basic-pace@rcs0.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113036v1/shard-rkl-5/igt@gem_exec_fair@basic-pace@rcs0.html * igt@gem_exec_reloc@basic-write-gtt-noreloc: - {shard-rkl}: [SKIP][11] ([i915#3281]) -> [PASS][12] +3 similar issues [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12605/shard-rkl-4/igt@gem_exec_reloc@basic-write-gtt-noreloc.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113036v1/shard-rkl-5/igt@gem_exec_reloc@basic-write-gtt-noreloc.html * igt@gem_mmap_gtt@coherency: - {shard-rkl}: [SKIP][13] ([fdo#111656]) -> [PASS][14] [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12605/shard-rkl-6/igt@gem_mmap_gtt@coherency.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113036v1/shard-rkl-5/igt@gem_mmap_gtt@coherency.html * igt@gem_partial_pwrite_pread@write-uncached: - {shard-rkl}: [SKIP][15] ([i915#3282]) -> [PASS][16] +1 similar issue [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12605/shard-rkl-4/igt@gem_partial_pwrite_pread@write-uncached.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113036v1/shard-rkl-5/igt@gem_partial_pwrite_pread@write-uncached.html * igt@gen9_exec_parse@allowed-all: - {shard-rkl}: [SKIP][17] ([i915#2527]) -> [PASS][18] +1 similar issue [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12605/shard-rkl-4/igt@gen9_exec_parse@allowed-all.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113036v1/shard-rkl-5/igt@gen9_exec_parse@allowed-all.html * igt@i915_pm_rc6_residency@rc6-idle@vcs0: - {shard-rkl}: [WARN][19] ([i915#2681]) -> [PASS][20] [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12605/shard-rkl-5/igt@i915_pm_rc6_residency@rc6-idle@vcs0.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113036v1/shard-rkl-6/igt@i915_pm_rc6_residency@rc6-idle@vcs0.html * igt@i915_pm_rpm@dpms-mode-unset-lpsp: - {shard-tglu}: [SKIP][21] ([i915#1397]) -> [PASS][22] [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12605/shard-tglu-6/igt@i915_pm_rpm@dpms-mode-unset-lpsp.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113036v1/shard-tglu-4/igt@i915_pm_rpm@dpms-mode-unset-lpsp.html * igt@i915_pm_rpm@system-suspend-modeset: - {shard-tglu}: [SKIP][23] ([i915#3547]) -> [PASS][24] [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12605/shard-tglu-6/igt@i915_pm_rpm@system-suspend-modeset.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113036v1/shard-tglu-4/igt@i915_pm_rpm@system-suspend-modeset.html * igt@kms_big_fb@x-tiled-16bpp-rotate-180: - {shard-tglu}: [SKIP][25] ([i915#1845] / [i915#7651]) -> [PASS][26] +3 similar issues [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12605/shard-tglu-6/igt@kms_big_fb@x-tiled-16bpp-rotate-180.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113036v1/shard-tglu-4/igt@kms_big_fb@x-tiled-16bpp-rotate-180.html * igt@kms_ccs@pipe-d-random-ccs-data-y_tiled_gen12_rc_ccs: - {shard-tglu}: [SKIP][27] ([i915#7651]) -> [PASS][28] +16 similar issues [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12605/shard-tglu-6/igt@kms_ccs@pipe-d-random-ccs-data-y_tiled_gen12_rc_ccs.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113036v1/shard-tglu-4/igt@kms_ccs@pipe-d-random-ccs-data-y_tiled_gen12_rc_ccs.html * igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy: - shard-glk: [FAIL][29] ([i915#72]) -> [PASS][30] [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12605/shard-glk3/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113036v1/shard-glk8/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy.html * igt@kms_draw_crc@fill-fb: - {shard-tglu}: [SKIP][31] ([i915#1845]) -> [PASS][32] +1 similar issue [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12605/shard-tglu-6/igt@kms_draw_crc@fill-fb.html [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113036v1/shard-tglu-4/igt@kms_draw_crc@fill-fb.html * igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@bc-hdmi-a1-hdmi-a2: - shard-glk: [FAIL][33] ([i915#79]) -> [PASS][34] [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12605/shard-glk6/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@bc-hdmi-a1-hdmi-a2.html [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113036v1/shard-glk7/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@bc-hdmi-a1-hdmi-a2.html * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-indfb-msflip-blt: - {shard-tglu}: [SKIP][35] ([i915#1849]) -> [PASS][36] +3 similar issues [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12605/shard-tglu-6/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-indfb-msflip-blt.html [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113036v1/shard-tglu-4/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-indfb-msflip-blt.html * igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-pwrite: - {shard-rkl}: [SKIP][37] ([i915#1849] / [i915#4098]) -> [PASS][38] +12 similar issues [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12605/shard-rkl-1/igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-pwrite.html [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113036v1/shard-rkl-6/igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-pwrite.html * igt@kms_plane@plane-position-hole@pipe-b-planes: - {shard-rkl}: [SKIP][39] ([i915#1849]) -> [PASS][40] +4 similar issues [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12605/shard-rkl-5/igt@kms_plane@plane-position-hole@pipe-b-planes.html [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113036v1/shard-rkl-6/igt@kms_plane@plane-position-hole@pipe-b-planes.html * igt@kms_psr@cursor_plane_onoff: - {shard-rkl}: [SKIP][41] ([i915#1072]) -> [PASS][42] +1 similar issue [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12605/shard-rkl-1/igt@kms_psr@cursor_plane_onoff.html [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113036v1/shard-rkl-6/igt@kms_psr@cursor_plane_onoff.html * igt@kms_universal_plane@cursor-fb-leak-pipe-d: - {shard-tglu}: [SKIP][43] ([fdo#109274]) -> [PASS][44] +2 similar issues [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12605/shard-tglu-6/igt@kms_universal_plane@cursor-fb-leak-pipe-d.html [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113036v1/shard-tglu-4/igt@kms_universal_plane@cursor-fb-leak-pipe-d.html * igt@kms_vblank@pipe-b-query-idle: - {shard-rkl}: [SKIP][45] ([i915#1845] / [i915#4098]) -> [PASS][46] +30 similar issues [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12605/shard-rkl-1/igt@kms_vblank@pipe-b-query-idle.html [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113036v1/shard-rkl-6/igt@kms_vblank@pipe-b-query-idle.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [fdo#103375]: https://bugs.freedesktop.org/show_bug.cgi?id=103375 [fdo#109274]: https://bugs.freedesktop.org/show_bug.cgi?id=109274 [fdo#109279]: https://bugs.freedesktop.org/show_bug.cgi?id=109279 [fdo#109280]: https://bugs.freedesktop.org/show_bug.cgi?id=109280 [fdo#109283]: https://bugs.freedesktop.org/show_bug.cgi?id=109283 [fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285 [fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289 [fdo#109291]: https://bugs.freedesktop.org/show_bug.cgi?id=109291 [fdo#109295]: https://bugs.freedesktop.org/show_bug.cgi?id=109295 [fdo#109309]: https://bugs.freedesktop.org/show_bug.cgi?id=109309 [fdo#109312]: https://bugs.freedesktop.org/show_bug.cgi?id=109312 [fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315 [fdo#109506]: https://bugs.freedesktop.org/show_bug.cgi?id=109506 [fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642 [fdo#110189]: https://bugs.freedesktop.org/show_bug.cgi?id=110189 [fdo#110723]: https://bugs.freedesktop.org/show_bug.cgi?id=110723 [fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068 [fdo#111614]: https://bugs.freedesktop.org/show_bug.cgi?id=111614 [fdo#111615]: https://bugs.freedesktop.org/show_bug.cgi?id=111615 [fdo#111644]: https://bugs.freedesktop.org/show_bug.cgi?id=111644 [fdo#111656]: https://bugs.freedesktop.org/show_bug.cgi?id=111656 [fdo#111825]: https://bugs.freedesktop.org/show_bug.cgi?id=111825 [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827 [fdo#112283]: https://bugs.freedesktop.org/show_bug.cgi?id=112283 [i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072 [i915#132]: https://gitlab.freedesktop.org/drm/intel/issues/132 [i915#1397]: https://gitlab.freedesktop.org/drm/intel/issues/1397 [i915#1722]: https://gitlab.freedesktop.org/drm/intel/issues/1722 [i915#1755]: https://gitlab.freedesktop.org/drm/intel/issues/1755 [i915#1769]: https://gitlab.freedesktop.org/drm/intel/issues/1769 [i915#1825]: https://gitlab.freedesktop.org/drm/intel/issues/1825 [i915#1839]: https://gitlab.freedesktop.org/drm/intel/issues/1839 [i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845 [i915#1849]: https://gitlab.freedesktop.org/drm/intel/issues/1849 [i915#2232]: https://gitlab.freedesktop.org/drm/intel/issues/2232 [i915#2437]: https://gitlab.freedesktop.org/drm/intel/issues/2437 [i915#2527]: https://gitlab.freedesktop.org/drm/intel/issues/2527 [i915#2575]: https://gitlab.freedesktop.org/drm/intel/issues/2575 [i915#2582]: https://gitlab.freedesktop.org/drm/intel/issues/2582 [i915#2587]: https://gitlab.freedesktop.org/drm/intel/issues/2587 [i915#2658]: https://gitlab.freedesktop.org/drm/intel/issues/2658 [i915#2672]: https://gitlab.freedesktop.org/drm/intel/issues/2672 [i915#2681]: https://gitlab.freedesktop.org/drm/intel/issues/2681 [i915#280]: https://gitlab.freedesktop.org/drm/intel/issues/280 [i915#284]: https://gitlab.freedesktop.org/drm/intel/issues/284 [i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842 [i915#2856]: https://gitlab.freedesktop.org/drm/intel/issues/2856 [i915#2920]: https://gitlab.freedesktop.org/drm/intel/issues/2920 [i915#2994]: https://gitlab.freedesktop.org/drm/intel/issues/2994 [i915#315]: https://gitlab.freedesktop.org/drm/intel/issues/315 [i915#3281]: https://gitlab.freedesktop.org/drm/intel/issues/3281 [i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282 [i915#3297]: https://gitlab.freedesktop.org/drm/intel/issues/3297 [i915#3323]: https://gitlab.freedesktop.org/drm/intel/issues/3323 [i915#3359]: https://gitlab.freedesktop.org/drm/intel/issues/3359 [i915#3458]: https://gitlab.freedesktop.org/drm/intel/issues/3458 [i915#3469]: https://gitlab.freedesktop.org/drm/intel/issues/3469 [i915#3546]: https://gitlab.freedesktop.org/drm/intel/issues/3546 [i915#3547]: https://gitlab.freedesktop.org/drm/intel/issues/3547 [i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555 [i915#3558]: https://gitlab.freedesktop.org/drm/intel/issues/3558 [i915#3591]: https://gitlab.freedesktop.org/drm/intel/issues/3591 [i915#3637]: https://gitlab.freedesktop.org/drm/intel/issues/3637 [i915#3638]: https://gitlab.freedesktop.org/drm/intel/issues/3638 [i915#3639]: https://gitlab.freedesktop.org/drm/intel/issues/3639 [i915#3689]: https://gitlab.freedesktop.org/drm/intel/issues/3689 [i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708 [i915#3734]: https://gitlab.freedesktop.org/drm/intel/issues/3734 [i915#3742]: https://gitlab.freedesktop.org/drm/intel/issues/3742 [i915#3886]: https://gitlab.freedesktop.org/drm/intel/issues/3886 [i915#3955]: https://gitlab.freedesktop.org/drm/intel/issues/3955 [i915#404]: https://gitlab.freedesktop.org/drm/intel/issues/404 [i915#4070]: https://gitlab.freedesktop.org/drm/intel/issues/4070 [i915#4078]: https://gitlab.freedesktop.org/drm/intel/issues/4078 [i915#4098]: https://gitlab.freedesktop.org/drm/intel/issues/4098 [i915#4270]: https://gitlab.freedesktop.org/drm/intel/issues/4270 [i915#4281]: https://gitlab.freedesktop.org/drm/intel/issues/4281 [i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312 [i915#4387]: https://gitlab.freedesktop.org/drm/intel/issues/4387 [i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613 [i915#4767]: https://gitlab.freedesktop.org/drm/intel/issues/4767 [i915#5176]: https://gitlab.freedesktop.org/drm/intel/issues/5176 [i915#5235]: https://gitlab.freedesktop.org/drm/intel/issues/5235 [i915#5286]: https://gitlab.freedesktop.org/drm/intel/issues/5286 [i915#5289]: https://gitlab.freedesktop.org/drm/intel/issues/5289 [i915#5325]: https://gitlab.freedesktop.org/drm/intel/issues/5325 [i915#5327]: https://gitlab.freedesktop.org/drm/intel/issues/5327 [i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533 [i915#5439]: https://gitlab.freedesktop.org/drm/intel/issues/5439 [i915#5461]: https://gitlab.freedesktop.org/drm/intel/issues/5461 [i915#5784]: https://gitlab.freedesktop.org/drm/intel/issues/5784 [i915#6095]: https://gitlab.freedesktop.org/drm/intel/issues/6095 [i915#6227]: https://gitlab.freedesktop.org/drm/intel/issues/6227 [i915#6247]: https://gitlab.freedesktop.org/drm/intel/issues/6247 [i915#6252]: https://gitlab.freedesktop.org/drm/intel/issues/6252 [i915#6334]: https://gitlab.freedesktop.org/drm/intel/issues/6334 [i915#6335]: https://gitlab.freedesktop.org/drm/intel/issues/6335 [i915#6412]: https://gitlab.freedesktop.org/drm/intel/issues/6412 [i915#6497]: https://gitlab.freedesktop.org/drm/intel/issues/6497 [i915#6524]: https://gitlab.freedesktop.org/drm/intel/issues/6524 [i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658 [i915#6590]: https://gitlab.freedesktop.org/drm/intel/issues/6590 [i915#6768]: https://gitlab.freedesktop.org/drm/intel/issues/6768 [i915#6944]: https://gitlab.freedesktop.org/drm/intel/issues/6944 [i915#6946]: https://gitlab.freedesktop.org/drm/intel/issues/6946 [i915#6953]: https://gitlab.freedesktop.org/drm/intel/issues/6953 [i915#7037]: https://gitlab.freedesktop.org/drm/intel/issues/7037 [i915#7052]: https://gitlab.freedesktop.org/drm/intel/issues/7052 [i915#7116]: https://gitlab.freedesktop.org/drm/intel/issues/7116 [i915#7118]: https://gitlab.freedesktop.org/drm/intel/issues/7118 [i915#72]: https://gitlab.freedesktop.org/drm/intel/issues/72 [i915#7456]: https://gitlab.freedesktop.org/drm/intel/issues/7456 [i915#7561]: https://gitlab.freedesktop.org/drm/intel/issues/7561 [i915#7651]: https://gitlab.freedesktop.org/drm/intel/issues/7651 [i915#7697]: https://gitlab.freedesktop.org/drm/intel/issues/7697 [i915#7707]: https://gitlab.freedesktop.org/drm/intel/issues/7707 [i915#7742]: https://gitlab.freedesktop.org/drm/intel/issues/7742 [i915#7828]: https://gitlab.freedesktop.org/drm/intel/issues/7828 [i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79 Build changes ------------- * Linux: CI_DRM_12605 -> Patchwork_113036v1 * Piglit: piglit_4509 -> None CI-20190529: 20190529 CI_DRM_12605: 1e863b59056127f55822b29a8f0cabf476806979 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_7123: 2b29e8ac07fbcfadc48b9d60e4d736a6e3b289ab @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git Patchwork_113036v1: 1e863b59056127f55822b29a8f0cabf476806979 @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113036v1/index.html [-- Attachment #2: Type: text/html, Size: 13210 bytes --] ^ permalink raw reply [flat|nested] 12+ messages in thread
end of thread, other threads:[~2023-01-20 22:46 UTC | newest] Thread overview: 12+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2023-01-18 15:52 [Intel-gfx] [PATCH v2 0/2] drm/i915/gt: Move LSC_CHICKEN_BIT* workarounds to correct function (Series) Gustavo Sousa 2023-01-18 15:52 ` [Intel-gfx] [PATCH v2 1/2] drm/i915/doc: Document where to implement register workarounds Gustavo Sousa 2023-01-19 21:56 ` Rodrigo Vivi 2023-01-18 15:52 ` [Intel-gfx] [PATCH v2 2/2] drm/i915/gt: Move LSC_CHICKEN_BIT* workarounds to correct function Gustavo Sousa 2023-01-19 21:57 ` Rodrigo Vivi 2023-01-19 22:24 ` Gustavo Sousa 2023-01-19 22:28 ` Vivi, Rodrigo 2023-01-19 23:03 ` Matt Roper 2023-01-20 22:46 ` Lucas De Marchi 2023-01-18 23:42 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/gt: Move LSC_CHICKEN_BIT* workarounds to correct function (Series) Patchwork 2023-01-18 23:57 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork 2023-01-19 22:02 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
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