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[2003:e4:1f20:1d00:f22f:74ff:fe1f:3a53]) by smtp.gmail.com with ESMTPSA id u20-20020a50a414000000b004a08c52a2f0sm538876edb.76.2023.01.26.02.35.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 26 Jan 2023 02:35:01 -0800 (PST) Date: Thu, 26 Jan 2023 11:34:59 +0100 From: Thierry Reding To: Svyatoslav Ryhel Cc: Rayagonda Kokatanur , Tom Warren , Marek Vasut , Maxim Schwalm , Dmitry Osipenko , Heinrich Schuchardt , Michal Simek , Stefan Roese , Eugen Hristev , Michael Walle , Simon Glass , Jim Liu , William Zhang , Rick Chen , Stefan Herbrechtsmeier , Andre Przywara , Jaehoon Chung , u-boot@lists.denx.de Subject: Re: [PATCH v6 0/3] Timer support for ARM Tegra Message-ID: References: <20230124065751.5973-1-clamor95@gmail.com> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="bTFeGozaYu6P/pem" Content-Disposition: inline In-Reply-To: User-Agent: Mutt/2.2.9 (2022-11-12) X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.6 at phobos.denx.de X-Virus-Status: Clean --bTFeGozaYu6P/pem Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Wed, Jan 25, 2023 at 05:41:08PM +0100, Thierry Reding wrote: > On Tue, Jan 24, 2023 at 08:57:48AM +0200, Svyatoslav Ryhel wrote: > > - ARM: tegra: remap clock_osc_freq for all Tegra family > > Enum clock_osc_freq was designed to use only with T20. > > This patch remaps it to use additional frequencies, added in > > T30+ SoC while maintaining backwards compatibility with T20. > >=20 > > - drivers: timer: add timer driver for ARMv7 based Tegra devices > > Add timer support for T20/T30/T114 and T124 based devices. > > Driver is based on DM, has device tree support and can be > > used on SPL and early boot stage. > >=20 > > - ARM: tegra: include timer as default option > > Enable TIMER as default option for all Tegra devices and > > enable TEGRA_TIMER for TEGRA_ARMV7_COMMON. Additionally > > enable SPL_TIMER if build as SPL part and drop deprecated > > configs from common header. > >=20 > > P. S. I have no arm64 Tegra and according to comment in=20 > > tegra-common.h > > Use the Tegra US timer on ARMv7, but the architected timer on ARMv8. > >=20 > > Svyatoslav Ryhel (3): > > ARM: tegra: remap clock_osc_freq for all Tegra family > > drivers: timer: add timer driver for ARMv7 based Tegra devices > > ARM: tegra: include timer as default option >=20 > This causes a regression on Tegra210 (Jetson TX1). I'm trying to > investigate, but it's complicated by the fact that I'm not getting out > any debug prints, so I suspect the issue is happening quite early. Alright, I managed to make this work on Tegra210 using the following patch on top of this series: --- >8 --- diff --git a/arch/arm/dts/tegra210.dtsi b/arch/arm/dts/tegra210.dtsi index a521a43d6cfd..ccb5a927da89 100644 --- a/arch/arm/dts/tegra210.dtsi +++ b/arch/arm/dts/tegra210.dtsi @@ -318,7 +318,7 @@ }; =20 timer@60005000 { - compatible =3D "nvidia,tegra210-timer", "nvidia,tegra20-timer"; + compatible =3D "nvidia,tegra210-timer", "nvidia,tegra30-timer", "nvidia,= tegra20-timer"; reg =3D <0x0 0x60005000 0x0 0x400>; interrupts =3D , , diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig index cc3f00e50128..b50eec5b8c9b 100644 --- a/arch/arm/mach-tegra/Kconfig +++ b/arch/arm/mach-tegra/Kconfig @@ -136,6 +136,7 @@ config TEGRA210 select TEGRA_PINCTRL select TEGRA_PMC select TEGRA_PMC_SECURE + select TEGRA_TIMER =20 config TEGRA186 bool "Tegra186 family" diff --git a/drivers/timer/tegra-timer.c b/drivers/timer/tegra-timer.c index d2d163cf3fef..235532ba8926 100644 --- a/drivers/timer/tegra-timer.c +++ b/drivers/timer/tegra-timer.c @@ -58,17 +58,26 @@ static notrace u64 tegra_timer_get_count(struct udevice= *dev) static int tegra_timer_probe(struct udevice *dev) { struct timer_dev_priv *uc_priv =3D dev_get_uclass_priv(dev); + enum clock_osc_freq freq; u32 usec_config, value; =20 /* Timer rate has to be set unconditionally */ uc_priv->clock_rate =3D TEGRA_TIMER_RATE; =20 + /* + * The microsecond timer runs off of clk_m on Tegra210, and clk_m + * runs at half the OSC, so fake this up. + */ + freq =3D clock_get_osc_freq(); + if (freq =3D=3D CLOCK_OSC_FREQ_38_4) + freq =3D CLOCK_OSC_FREQ_19_2; + /* * Configure microsecond timers to have 1MHz clock * Config register is 0xqqww, where qq is "dividend", ww is "divisor" * Uses n+1 scheme */ - switch (clock_get_osc_freq()) { + switch (freq) { case CLOCK_OSC_FREQ_13_0: usec_config =3D 0x000c; /* (12+1)/(0+1) */ break; @@ -113,6 +122,7 @@ static const struct udevice_id tegra_timer_ids[] =3D { { .compatible =3D "nvidia,tegra30-timer" }, { .compatible =3D "nvidia,tegra114-timer" }, { .compatible =3D "nvidia,tegra124-timer" }, + { .compatible =3D "nvidia,tegra210-timer" }, { } }; --- >8 --- I've also tested this on Tegra186, though no additional changes were needed since Tegra186 doesn't use the Tegra timer. With the above folded in, the series is: Tested-by: Thierry Reding --bTFeGozaYu6P/pem Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- iQIzBAABCAAdFiEEiOrDCAFJzPfAjcif3SOs138+s6EFAmPSV1AACgkQ3SOs138+ s6G/Cw/+L1pgXURYs6WQyELNVQhMErPcM3OJu9j5HYqjEoNz68+BPf9BSdMok88v McxS7Dzk3knjg/LvfU0FEmqKc2wixxtB9vUnG2j0nkWOPnSj9UrY1590wYab/Kxn JKPuzsTUgk8qgTy7QRFMWHwJxFJzoVdOYgHyhRPW0vbzOEg9rIahBGcXPo3mlneV KcXi+Nzto8MAmuVZ6lN6B/1oZ7oj3NXzjAJszrL7zFd2tEbIa/4yIXpxr7NUhjTH +5JzDhbZ09H3NxE2siWl7/VA54CD6OXIpCJ6zpgEp9K+SGHEolO14zH+hHTMQyDQ 0DQMKe2kGpVyFMZ6FvGt1auG/BLtV32fkA0OimCh8AI5irv+HLkN4V/9hm7W6VGZ uuKmVEPTQSRKn4RtsE2d2Ti/TPBtO1sSGd42ZRm58E8uUEoP107mg2F/1NP3Nab4 EYtznFLIj5/lGIpxc7MshORoYBSYccYi+/SA2A8G3/MMR0zdPq5I0wj2R0jNhwIz XbQZi5osOavpeTv0YoGsj0TH8bx3qKA4clOqcQC6HkhM97myatLh9WpGpQc7kUyI 1F4WSg7AwMNZfVbH/A/WXKsmf3Dya/ZKApc5oXRwjdKe525S+g4SiCe34grS2Hgs 050KoUSSur8e+4wdEAVYEOdRmRRAhGbfH04+RC6FSk0hYcX3HXY= =IGCj -----END PGP SIGNATURE----- --bTFeGozaYu6P/pem--