From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 0EBEBC05027 for ; Thu, 26 Jan 2023 17:58:23 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 71B6385734; Thu, 26 Jan 2023 18:58:20 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="botLFnDl"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id CE6238573D; Thu, 26 Jan 2023 18:58:18 +0100 (CET) Received: from mail-ej1-x634.google.com (mail-ej1-x634.google.com [IPv6:2a00:1450:4864:20::634]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 3C6E3856D3 for ; Thu, 26 Jan 2023 18:58:15 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=thierry.reding@gmail.com Received: by mail-ej1-x634.google.com with SMTP id k4so1746297eje.1 for ; Thu, 26 Jan 2023 09:58:15 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=user-agent:in-reply-to:content-disposition:mime-version:references :message-id:subject:cc:to:from:date:from:to:cc:subject:date :message-id:reply-to; bh=1p8QHcYO/lkForh/yX0oDhMuOtpLSI6ZeXWaAPS2Re8=; b=botLFnDlHG05QkQ27udDPRzgfzZHl9hGCMGLWtqJF2B+CbC0VvTMFx/eiM6J+yzCRt PR6F48y/h/hS/4DmQBkQx6O8iaFzaF8Q9+5hmoTJvlyw8TqUIgofsRKdHD2fcvWOnKLf ggtsjxM/xNn6zmShdmW/nKPX3mfiXbQSwKFw5O2txqUpDhuC/WpnZ0sTbMzLq/lbIRb1 t9vTIopxfFZ99DCW0MviU2u82SxYl2XDccGMZxBaUdoLeoDOoLjcJmdDPCYFLR4rDKJw UC2N6VVkYCIM2ksOiuv8DSElvDYMfMaTECAUJc9GFReCSCzab2Liypk0Du7PDzz6VlEf pcSA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=user-agent:in-reply-to:content-disposition:mime-version:references :message-id:subject:cc:to:from:date:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=1p8QHcYO/lkForh/yX0oDhMuOtpLSI6ZeXWaAPS2Re8=; b=4/zSinA0iiceMq9uz9YjjLUIHKl1nKudByI+nOuSR37gDDktSSF0/5F5GRRTQ/pjag xrvY5pFqWVsJ3urydtTevvNf/9UV1P9blTpO4HflECwMRKbiPY8SLVKU4wh/nJ37qaNi hJ7+TjZjqTDIBx5oNFZqx3MRe8h90V0IWJbSyQzwrLINhLUWUh1JS1JFtyZ0y83/nhcU ByZNBwPqtZcapJ+m6Cpa1+4kOEc5MvknUyt6N+RkA+R33GePji9oTAsGfAiQzEdHg5Z1 MyDvyC1r3oQJAHqgdPbwEnU+0TPSGOoyKZySc8GZmSb8CfeCupfHHqya6+FWpiull93l VSww== X-Gm-Message-State: AFqh2kr7ipTk0/DzJyGKZZBjixgpFAMmNPwYNc928ouHe4Jas47Y6Cuf UL2uoWNF9wYzH0OVCEqalKI= X-Google-Smtp-Source: AMrXdXt4meWAkEB40CAyYQOQ/U8Z+Ap/fo4kEmaYgOqM+jZ4fibHA0lKVjO1iIHYl4J7kWpL4zNcbw== X-Received: by 2002:a17:906:70c7:b0:84c:a863:ebe6 with SMTP id g7-20020a17090670c700b0084ca863ebe6mr31021546ejk.43.1674755894654; Thu, 26 Jan 2023 09:58:14 -0800 (PST) Received: from orome (p200300e41f201d00f22f74fffe1f3a53.dip0.t-ipconnect.de. [2003:e4:1f20:1d00:f22f:74ff:fe1f:3a53]) by smtp.gmail.com with ESMTPSA id o25-20020a170906861900b008675df83251sm904759ejx.34.2023.01.26.09.58.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 26 Jan 2023 09:58:14 -0800 (PST) Date: Thu, 26 Jan 2023 18:58:12 +0100 From: Thierry Reding To: Svyatoslav Ryhel Cc: Tom Warren , Rayagonda Kokatanur , Marek Vasut , Maxim Schwalm , Dmitry Osipenko , Heinrich Schuchardt , Michal Simek , Stefan Roese , Eugen Hristev , Michael Walle , Simon Glass , Jim Liu , William Zhang , Rick Chen , Stefan Herbrechtsmeier , Andre Przywara , Jaehoon Chung , "u-boot@lists.denx.de" Subject: Re: [PATCH v6 0/3] Timer support for ARM Tegra Message-ID: References: <20230124065751.5973-1-clamor95@gmail.com> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="WxUXfOj+TNb8hFt9" Content-Disposition: inline In-Reply-To: User-Agent: Mutt/2.2.9 (2022-11-12) X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.6 at phobos.denx.de X-Virus-Status: Clean --WxUXfOj+TNb8hFt9 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Thu, Jan 26, 2023 at 07:12:34PM +0200, Svyatoslav Ryhel wrote: > I may implement changes of Thierry Reding in a proper form as a > separate patch or include in existing (depends on his choice). I think it's ultimately better if this is properly integrated into the series because the series would remain bisectible. If the existing series is applied as-is, we have a few patches in the middle during which Tegra210 is unusable. So if we ever have to track down a regression that might be problematic. It's not a big deal since we've rarely had regressions in U-Boot. It's ultimately up to Tom to decide how he wants to handle this. If you send out another series, can you please add me on Cc so I don't miss it? Thanks, Thierry > The only thing I need to know is if ALL known T210 devices use > 19.2MHz as calibration clock for timer? >=20 > Best regards. > Svyatoslav R. >=20 > =D1=87=D1=82, 26 =D1=81=D1=96=D1=87. 2023 =D1=80. =D0=BE 18:50 Tom Warren= =D0=BF=D0=B8=D1=88=D0=B5: > > > > Thanks for testing T210/T186, Thierry. > > > > I had Svyatoslav's patches ready to go for a PR yesterday, so I'll need= either a patch from you for the T210 changes that I can apply on top of hi= s, or I'll need Svyatoslav to adopt your changes as a 4th patch in his seri= es. Once I have that and can pass buildman OK, I'll be ready to send a PR t= o TomR. > > > > Tom > > > > -----Original Message----- > > From: Thierry Reding > > Sent: Thursday, January 26, 2023 4:41 AM > > To: Svyatoslav Ryhel > > Cc: Rayagonda Kokatanur ; Tom Warren = ; Marek Vasut ; Maxim Schwalm ; Dmitry Osipenko ; Heinrich Schuchardt ; Michal Simek ; Stefan Roese ; Eugen Hristev ; Michael Walle ; Simon Glass ; Jim Liu = ; William Zhang ; Rick Chen ; Stefan Herbrechtsmeier ; Andre P= rzywara ; Jaehoon Chung ; u= -boot@lists.denx.de > > Subject: Re: [PATCH v6 0/3] Timer support for ARM Tegra > > > > On Thu, Jan 26, 2023 at 11:34:59AM +0100, Thierry Reding wrote: > > > On Wed, Jan 25, 2023 at 05:41:08PM +0100, Thierry Reding wrote: > > > > On Tue, Jan 24, 2023 at 08:57:48AM +0200, Svyatoslav Ryhel wrote: > > > > > - ARM: tegra: remap clock_osc_freq for all Tegra family Enum > > > > > clock_osc_freq was designed to use only with T20. > > > > > This patch remaps it to use additional frequencies, added in > > > > > T30+ SoC while maintaining backwards compatibility with T20. > > > > > > > > > > - drivers: timer: add timer driver for ARMv7 based Tegra devices > > > > > Add timer support for T20/T30/T114 and T124 based devices. > > > > > Driver is based on DM, has device tree support and can be used on > > > > > SPL and early boot stage. > > > > > > > > > > - ARM: tegra: include timer as default option Enable TIMER as > > > > > default option for all Tegra devices and enable TEGRA_TIMER for > > > > > TEGRA_ARMV7_COMMON. Additionally enable SPL_TIMER if build as SPL > > > > > part and drop deprecated configs from common header. > > > > > > > > > > P. S. I have no arm64 Tegra and according to comment in > > > > > tegra-common.h Use the Tegra US timer on ARMv7, but the > > > > > architected timer on ARMv8. > > > > > > > > > > Svyatoslav Ryhel (3): > > > > > ARM: tegra: remap clock_osc_freq for all Tegra family > > > > > drivers: timer: add timer driver for ARMv7 based Tegra devices > > > > > ARM: tegra: include timer as default option > > > > > > > > This causes a regression on Tegra210 (Jetson TX1). I'm trying to > > > > investigate, but it's complicated by the fact that I'm not getting > > > > out any debug prints, so I suspect the issue is happening quite ear= ly. > > > > > > Alright, I managed to make this work on Tegra210 using the following > > > patch on top of this series: > > > > > > --- >8 --- > > > diff --git a/arch/arm/dts/tegra210.dtsi b/arch/arm/dts/tegra210.dtsi > > > index a521a43d6cfd..ccb5a927da89 100644 > > > --- a/arch/arm/dts/tegra210.dtsi > > > +++ b/arch/arm/dts/tegra210.dtsi > > > @@ -318,7 +318,7 @@ > > > }; > > > > > > timer@60005000 { > > > - compatible =3D "nvidia,tegra210-timer", "nvidia,tegra20= -timer"; > > > + compatible =3D "nvidia,tegra210-timer", "nvidia,tegra30= -timer", > > > +"nvidia,tegra20-timer"; > > > reg =3D <0x0 0x60005000 0x0 0x400>; > > > interrupts =3D , > > > , diff --git > > > a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig index > > > cc3f00e50128..b50eec5b8c9b 100644 > > > --- a/arch/arm/mach-tegra/Kconfig > > > +++ b/arch/arm/mach-tegra/Kconfig > > > @@ -136,6 +136,7 @@ config TEGRA210 > > > select TEGRA_PINCTRL > > > select TEGRA_PMC > > > select TEGRA_PMC_SECURE > > > + select TEGRA_TIMER > > > > > > config TEGRA186 > > > bool "Tegra186 family" > > > diff --git a/drivers/timer/tegra-timer.c b/drivers/timer/tegra-timer.c > > > index d2d163cf3fef..235532ba8926 100644 > > > --- a/drivers/timer/tegra-timer.c > > > +++ b/drivers/timer/tegra-timer.c > > > @@ -58,17 +58,26 @@ static notrace u64 tegra_timer_get_count(struct > > > udevice *dev) static int tegra_timer_probe(struct udevice *dev) { > > > struct timer_dev_priv *uc_priv =3D dev_get_uclass_priv(dev); > > > + enum clock_osc_freq freq; > > > u32 usec_config, value; > > > > > > /* Timer rate has to be set unconditionally */ > > > uc_priv->clock_rate =3D TEGRA_TIMER_RATE; > > > > > > + /* > > > + * The microsecond timer runs off of clk_m on Tegra210, and clk= _m > > > + * runs at half the OSC, so fake this up. > > > + */ > > > + freq =3D clock_get_osc_freq(); > > > + if (freq =3D=3D CLOCK_OSC_FREQ_38_4) > > > + freq =3D CLOCK_OSC_FREQ_19_2; > > > + > > > /* > > > * Configure microsecond timers to have 1MHz clock > > > * Config register is 0xqqww, where qq is "dividend", ww is "di= visor" > > > * Uses n+1 scheme > > > */ > > > - switch (clock_get_osc_freq()) { > > > + switch (freq) { > > > case CLOCK_OSC_FREQ_13_0: > > > usec_config =3D 0x000c; /* (12+1)/(0+1) */ > > > break; > > > @@ -113,6 +122,7 @@ static const struct udevice_id tegra_timer_ids[] = =3D { > > > { .compatible =3D "nvidia,tegra30-timer" }, > > > { .compatible =3D "nvidia,tegra114-timer" }, > > > { .compatible =3D "nvidia,tegra124-timer" }, > > > + { .compatible =3D "nvidia,tegra210-timer" }, > > > { } > > > }; > > > --- >8 --- > > > > > > I've also tested this on Tegra186, though no additional changes were > > > needed since Tegra186 doesn't use the Tegra timer. > > > > > > With the above folded in, the series is: > > > > > > Tested-by: Thierry Reding > > > > I've also tested your series with the above on Tegra30 (Beaver) and > > Tegra124 (Jetson TK1), both seem to work fine. > > > > Thierry --WxUXfOj+TNb8hFt9 Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- iQIzBAABCAAdFiEEiOrDCAFJzPfAjcif3SOs138+s6EFAmPSvzQACgkQ3SOs138+ s6FCZA//b+r4X4aFpEZlPaZ5CDc3WfO6aa/XarqQpTo1bdF/bxWooeblOL6JJ6Gq maHRFeDYvB6Y2CQdBjUk3FDC6uj8APB6LQSVWPPH+XXfmP8gnQhkKZNIAOAFc7if NYakLCxCgVW9B/JMlaLMdTStnaEYeS8wF+CRFNJ5uYwPU2lupqurFHN5Q4o3vlER B/7Sr9fVgnbSiTa4FGd2YNBcoiQUVFvjiLHPKuSilmayMVHoqVF+dxJfA6avn1im A+KnTb0QdBU95fwsO7e4iH8bwpELNfRjwcr1s97K8AOOraBt53hCW7Ok6UjtNJB6 Wka2Zhssv/1YHgfgQg08xykrVVdBxjK4y098r0ylAxJs4jHrFAp7u6A6oM8QFbXp 1ZmNTnHnDDxidAZBjoiYjmyeoVsJtX0s4IhGNwDF8/xGyIjetlKf2vPJMzUInaiX +Sh90vZ9BpbSiM00XBCa830HEosiEtwIzB9FFr/r/AwH7GEGramvedwU0EnjE+bE R3YesknHs1BzNmydAEXu/lrIRxoKbKbhTnCSE+D29RRQQSSKObHKf7sZwSOrfbrI w0qWZFAPQ1TtTI+wbgY8nQm7I7p+Flc5WPwhxFwQ3xdS7U9wFnRQz7Mn4fvkUuV9 3LxUzoMsLWEuV5IhaldW81I87fh/abp7I58FkA2qlqW1pvS6eHg= =skRO -----END PGP SIGNATURE----- --WxUXfOj+TNb8hFt9--