From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 70442C05027 for ; Thu, 26 Jan 2023 14:52:32 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232377AbjAZOwb (ORCPT ); Thu, 26 Jan 2023 09:52:31 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57668 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232376AbjAZOw1 (ORCPT ); Thu, 26 Jan 2023 09:52:27 -0500 Received: from ams.source.kernel.org (ams.source.kernel.org [IPv6:2604:1380:4601:e00::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 04A2A6BBC3 for ; Thu, 26 Jan 2023 06:52:04 -0800 (PST) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id A64AAB81D69 for ; Thu, 26 Jan 2023 14:52:02 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id E0DDFC4339C; Thu, 26 Jan 2023 14:51:58 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1674744721; bh=+NgsKVFUUhzqZAcR6UeDOLqBlEm20x5jmNxv9nwefCA=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=S7BYzncGEDBSCuk1OGgluf7AEhoUvpM9AC9aVGG2jXNeLEjFR8YufM4O2yuWr8CY7 40X4O/y+Tpb+VhSqI2QTZ+KNSN8l8pbwftAJna+56sIYfsAt+kn747NiPLqFAYuP3B cEDqUvyC23UY9bnR0W4eRj5wSzDtuw8/IpBH6Wy97xKOJjOz4291gehrfDhFQsOFwZ 2BYMBcuMSCP5dIclv0T7TkijZTekO41zfaM/fx2dhp1KPzl3Cehi49LJCUzeZprVmE Y9cKJ6/x2SHeX9CcpiiQ5LxNDopzUQ1r7MWjh03aC9RFXkr39irxIiq0ZwBTW3JCKN kYsvTa+1gC8Ww== Date: Thu, 26 Jan 2023 14:51:55 +0000 From: Lee Jones To: Biju Das Cc: Daniel Lezcano , Philipp Zabel , Thomas Gleixner , Geert Uytterhoeven , Chris Paterson , Prabhakar Mahadev Lad , "linux-renesas-soc@vger.kernel.org" , Rob Herring , Krzysztof Kozlowski Subject: Re: [PATCH v11 2/6] clocksource/drivers: Add Renesas RZ/G2L MTU3a core driver Message-ID: References: <20230113161753.1073706-1-biju.das.jz@bp.renesas.com> <20230113161753.1073706-3-biju.das.jz@bp.renesas.com> <9f722f37-15da-0384-c059-a4af0f1dab10@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: Precedence: bulk List-ID: X-Mailing-List: linux-renesas-soc@vger.kernel.org On Thu, 26 Jan 2023, Biju Das wrote: > Hi Daniel, > > + Rob and Krzysztof Kozlowski > > > -----Original Message----- > > From: Daniel Lezcano > > Sent: Thursday, January 26, 2023 10:53 AM > > To: Biju Das ; Philipp Zabel > > > > Cc: Thomas Gleixner ; Geert Uytterhoeven > > ; Chris Paterson ; > > Prabhakar Mahadev Lad ; linux- > > renesas-soc@vger.kernel.org; Lee Jones > > Subject: Re: [PATCH v11 2/6] clocksource/drivers: Add Renesas RZ/G2L MTU3a > > core driver > > > > On 13/01/2023 17:17, Biju Das wrote: > > > > [ ... ] > > > > > +config RZ_MTU3 > > > + bool "Renesas RZ/G2L MTU3a core driver" > > > + select MFD_CORE > > > + depends on (ARCH_RZG2L && OF) || COMPILE_TEST > > > + help > > > + Select this option to enable Renesas RZ/G2L MTU3a core driver for > > > + the Multi-Function Timer Pulse Unit 3 (MTU3a) hardware available > > > + on SoCs from Renesas. The core driver shares the clk and channel > > > + register access for the other child devices like Counter, PWM, > > > + Clock Source, and Clock event. > > > > Do you really want to have this option manually selectable? Usually we try > > to avoid that and keep a silent option which is selected by the platform > > config. > > For critical drivers like CPG, Pinctrl we enable it by default by silent option in platform config. > For the others we add it to defconfig, once the device tree support is available. > > > > > > [ ... ] > > > > > + > > > + ret = mfd_add_devices(&pdev->dev, 0, rz_mtu3_devs, > > > + ARRAY_SIZE(rz_mtu3_devs), NULL, 0, NULL); > > > + if (ret < 0) > > > + goto err_assert; > > > + > > > + return devm_add_action_or_reset(&pdev->dev, rz_mtu3_reset_assert, > > > + &pdev->dev); > > > + > > > +err_assert: > > > + reset_control_assert(ddata->rstc); > > > + return ret; > > > +} > > > > I'm not sure this driver falls under the clocksource umbrella but under > > mfd [cc'ed Lee Jones] > > > > > Please find [1], > > After a long discussion with dt maintainers, counter maintainer, MFD maintainer and PWM maintainer, it is concluded to > Add the core driver to timer subsystem. Which is fine. However, you cannot then use the MFD API. > [1] https://patchwork.kernel.org/project/linux-renesas-soc/patch/20221010145222.1047748-2-biju.das.jz@bp.renesas.com/ "The TL;DR is: if you're not using the MFD Core (and including mfd/core.h), it's not an MFD. You *could* split this up into its component parts, place them into their own subsystems and use an MFD core driver to register them all, but as Thierry says, this is not a hard requirement either." -- Lee Jones [李琼斯]