Re: [Intel-gfx] [PATCH v2] drm/i915: implement async_flip mode per plane tracking

["Ville Syrjälä" <ville.syrjala@linux.intel.com>]

On Thu, Jan 26, 2023 at 07:14:30PM +0100, Andrzej Hajda wrote:
> On 24.01.2023 15:02, Ville Syrjälä wrote:
> > On Wed, Jan 11, 2023 at 05:22:47PM +0100, Andrzej Hajda wrote:
> >> Current implementation of async flip w/a relies on assumption that
> >> previous atomic commit contains valid information if async_flip is still
> >> enabled on the plane. It is incorrect. If previous commit did not modify
> >> the plane its state->uapi.async_flip can be false. As a result DMAR/PIPE
> >> errors can be observed:
> >> i915 0000:00:02.0: [drm] *ERROR* Fault errors on pipe A: 0x00000080
> >> i915 0000:00:02.0: [drm] *ERROR* Fault errors on pipe A: 0x00000080
> >> DMAR: DRHD: handling fault status reg 2
> >> DMAR: [DMA Read NO_PASID] Request device [00:02.0] fault addr 0x0 [fault reason 0x06] PTE Read access is not set
> >>
> >> v2: update async_flip_planes in more reliable places (Ville)
> >>
> >> Signed-off-by: Andrzej Hajda <andrzej.hajda@intel.com>
> >> ---
> >>   drivers/gpu/drm/i915/display/intel_atomic_plane.c  | 5 ++++-
> >>   drivers/gpu/drm/i915/display/intel_display.c       | 7 ++++---
> >>   drivers/gpu/drm/i915/display/intel_display_types.h | 3 +++
> >>   3 files changed, 11 insertions(+), 4 deletions(-)
> >>
> >> diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> >> index 10e1fc9d069827..3f1b1548ede025 100644
> >> --- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> >> +++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> >> @@ -362,6 +362,7 @@ void intel_plane_set_invisible(struct intel_crtc_state *crtc_state,
> >>   	crtc_state->scaled_planes &= ~BIT(plane->id);
> >>   	crtc_state->nv12_planes &= ~BIT(plane->id);
> >>   	crtc_state->c8_planes &= ~BIT(plane->id);
> >> +	crtc_state->async_flip_planes &= ~BIT(plane->id);
> >>   	crtc_state->data_rate[plane->id] = 0;
> >>   	crtc_state->data_rate_y[plane->id] = 0;
> >>   	crtc_state->rel_data_rate[plane->id] = 0;
> >> @@ -581,8 +582,10 @@ static int intel_plane_atomic_calc_changes(const struct intel_crtc_state *old_cr
> >>   			 intel_plane_is_scaled(new_plane_state))))
> >>   		new_crtc_state->disable_lp_wm = true;
> >>   
> >> -	if (intel_plane_do_async_flip(plane, old_crtc_state, new_crtc_state))
> >> +	if (intel_plane_do_async_flip(plane, old_crtc_state, new_crtc_state)) {
> >>   		new_crtc_state->do_async_flip = true;
> >> +		new_crtc_state->async_flip_planes |= BIT(plane->id);
> >> +	}
> > 
> > intel_modeset_all_pipes() and intel_color_add_affected_planes() would
> > need to clear this stuff as well. Can't immediately think of other
> 
> I am not familiar with the display, so forgive me being verbose in 
> verification of your comments :)
> 1. In case of intel_modeset_all_pipes
>   for every crtc: crtc_state->async_flip_planes = 0;
> 2. In case of intel_color_add_affected_planes:
>   for every plane: new_crtc_state->async_flip_planes &= ~BIT(plane->id);

I think I'd do async_flip_planes=0 in both case, and also
do_async_flip=false. Guarantees we don't end up in some funny
state where some planes would want to do an async update
and some other ones a sync update.

> Are the changes OK?
> 
> > places that need the same treatment (the nv12 plane stuff I believe
> > should be fine without this since we should be rejecting async flips
> > with planar formats).
> 
> The driver is quite big and I quickly get lost when lurking into it, so 
> hard to comment it :)
> 
> > 
> > Though I think that is still going to have annoying ping-pong
> > for the the wm/ddb optimizations whenever there are internal
> > sync plane updates injected between async flips. I think to
> 
> Hmm, I hoped, that since intel_crtc_duplicate_state preserves 
> async_flip_planes ping-pong shouldn't happen.
> 
> > sort that out fully we'd need to start tracking the last uapi
> > async flip state for each plane.
> 
> 
> I hoped async_flip_planes should serve it, modulo it is not fully clear 
> to me when to switch async_flip. Enabling async flip is quite clear 
> (requested by user), but disabling:
> - full modeset,
> - sync fb update,
> - plane disable,
> - cases mentioned above,
> - ?

That reminds me that skl_{ddb,wm}_add_affected_planes() should
also disable async flips.

> 
> Is it OK to send next version with added clearing code in 
> intel_modeset_all_pipes and intel_color_add_affected_planes ?

Yeah, I think that should be good enough improvement for the moment.

> 
> Regards
> Andrzej
> 
> > 
> >>   
> >>   	return 0;
> >>   }
> >> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> >> index e75b9b2a0e015a..e1c3b1b0b6a8f1 100644
> >> --- a/drivers/gpu/drm/i915/display/intel_display.c
> >> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> >> @@ -1303,7 +1303,8 @@ static void intel_crtc_async_flip_disable_wa(struct intel_atomic_state *state,
> >>   		intel_atomic_get_old_crtc_state(state, crtc);
> >>   	const struct intel_crtc_state *new_crtc_state =
> >>   		intel_atomic_get_new_crtc_state(state, crtc);
> >> -	u8 update_planes = new_crtc_state->update_planes;
> >> +	u8 disable_async_flip_planes = old_crtc_state->async_flip_planes &
> >> +				       ~new_crtc_state->async_flip_planes;
> >>   	const struct intel_plane_state *old_plane_state;
> >>   	struct intel_plane *plane;
> >>   	bool need_vbl_wait = false;
> >> @@ -1312,7 +1313,7 @@ static void intel_crtc_async_flip_disable_wa(struct intel_atomic_state *state,
> >>   	for_each_old_intel_plane_in_state(state, plane, old_plane_state, i) {
> >>   		if (plane->need_async_flip_disable_wa &&
> >>   		    plane->pipe == crtc->pipe &&
> >> -		    update_planes & BIT(plane->id)) {
> >> +		    disable_async_flip_planes & BIT(plane->id)) {
> >>   			/*
> >>   			 * Apart from the async flip bit we want to
> >>   			 * preserve the old state for the plane.
> >> @@ -1429,7 +1430,7 @@ static void intel_pre_plane_update(struct intel_atomic_state *state,
> >>   	 * WA for platforms where async address update enable bit
> >>   	 * is double buffered and only latched at start of vblank.
> >>   	 */
> >> -	if (old_crtc_state->uapi.async_flip && !new_crtc_state->uapi.async_flip)
> >> +	if (old_crtc_state->async_flip_planes & ~new_crtc_state->async_flip_planes)
> >>   		intel_crtc_async_flip_disable_wa(state, crtc);
> >>   }
> >>   
> >> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> >> index 32e8b2fc3cc642..61b1a0ec3dede1 100644
> >> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> >> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> >> @@ -1248,6 +1248,9 @@ struct intel_crtc_state {
> >>   	/* bitmask of planes that will be updated during the commit */
> >>   	u8 update_planes;
> >>   
> >> +	/* bitmask of planes with async flip active */
> >> +	u8 async_flip_planes;
> >> +
> >>   	u8 framestart_delay; /* 1-4 */
> >>   	u8 msa_timing_delay; /* 0-3 */
> >>   
> >> -- 
> >> 2.34.1
> > 

-- 
Ville Syrjälä
Intel