From: Leo Liang <ycliang@andestech.com>
To: Yu Chien Peter Lin <peterlin@andestech.com>
Cc: <u-boot@lists.denx.de>, <rick@andestech.com>
Subject: Re: [PATCH 03/11] board: AndesTech: ax25-ae350.c: Enable v5l2-cache in spl_board_init()
Date: Tue, 31 Jan 2023 06:59:27 +0000 [thread overview]
Message-ID: <Y9i8T3PNbUi2a6R2@ubuntu01> (raw)
In-Reply-To: <20230119070544.7423-4-peterlin@andestech.com>
On Thu, Jan 19, 2023 at 03:05:36PM +0800, Yu Chien Peter Lin wrote:
> The L2-cache is not enabled currently, the enbale_caches() will call
> the v5l2_enable() callback to enable it in SPL.
>
> Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
> ---
> board/AndesTech/ax25-ae350/ax25-ae350.c | 17 +++++++++--------
> 1 file changed, 9 insertions(+), 8 deletions(-)
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
next prev parent reply other threads:[~2023-01-31 6:59 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-01-19 7:05 [PATCH 00/11] cache operation cleanups for Andes AE350 platform Yu Chien Peter Lin
2023-01-19 7:05 ` [PATCH 01/11] riscv: global_data.h: Correct the comment for PLICSW Yu Chien Peter Lin
2023-01-31 6:39 ` Leo Liang
[not found] ` <PU1PR03MB2997857A35E6E20FAD5C032AC1D19@PU1PR03MB2997.apcprd03.prod.outlook.com>
2023-02-01 3:37 ` Rick Chen
2023-01-19 7:05 ` [PATCH 02/11] riscv: Remove redundant Kconfig "RISCV_NDS_CACHE" Yu Chien Peter Lin
2023-01-31 6:41 ` Leo Liang
[not found] ` <PU1PR03MB29972FC9DEB3F9F0889143BAC1D19@PU1PR03MB2997.apcprd03.prod.outlook.com>
2023-02-01 5:20 ` Rick Chen
2023-01-19 7:05 ` [PATCH 03/11] board: AndesTech: ax25-ae350.c: Enable v5l2-cache in spl_board_init() Yu Chien Peter Lin
2023-01-31 6:59 ` Leo Liang [this message]
[not found] ` <PU1PR03MB29972FEA49428A23FA2D8786C1D19@PU1PR03MB2997.apcprd03.prod.outlook.com>
2023-02-01 5:23 ` Rick Chen
2023-01-19 7:05 ` [PATCH 04/11] driver: cache: cache-v5l2: Update memory-mapped scheme to support Gen2 platform Yu Chien Peter Lin
2023-01-31 7:01 ` Leo Liang
2023-01-19 7:05 ` [PATCH 05/11] riscv: cpu: ax25: Simplify cache enabling logic in harts_early_init() Yu Chien Peter Lin
2023-01-31 7:07 ` Leo Liang
2023-01-31 15:49 ` Yu-Chien Peter Lin
2023-01-19 7:05 ` [PATCH 06/11] riscv: ae350: dts: Update L2 cache compatible string Yu Chien Peter Lin
2023-01-31 7:07 ` Leo Liang
2023-01-19 7:05 ` [PATCH 07/11] riscv: ax25: cache.c: Cleanups to L1/L2 cache function used in SPL Yu Chien Peter Lin
2023-01-31 7:09 ` Leo Liang
2023-01-19 7:05 ` [PATCH 08/11] configs: ae350: Enable v5l2 cache for AE350 platforms Yu Chien Peter Lin
2023-01-31 7:17 ` Leo Liang
[not found] ` <PU1PR03MB299711E617F0F0969237426EC1D19@PU1PR03MB2997.apcprd03.prod.outlook.com>
2023-02-01 5:32 ` Rick Chen
2023-01-19 7:05 ` [PATCH 09/11] configs: ae350: Increase maximum retry count " Yu Chien Peter Lin
2023-01-31 7:18 ` Leo Liang
2023-01-19 7:05 ` [PATCH 10/11] configs: ae350: Display CPU and board info " Yu Chien Peter Lin
2023-01-31 7:18 ` Leo Liang
2023-01-19 7:05 ` [PATCH 11/11] driver: cache-v5l2: Fix type casting warning on RV32 Yu Chien Peter Lin
2023-01-31 7:19 ` Leo Liang
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=Y9i8T3PNbUi2a6R2@ubuntu01 \
--to=ycliang@andestech.com \
--cc=peterlin@andestech.com \
--cc=rick@andestech.com \
--cc=u-boot@lists.denx.de \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.