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From: Leo Liang <ycliang@andestech.com>
To: Nikita Shubin <nikita.shubin@maquefel.me>
Cc: Nikita Shubin <n.shubin@yadro.com>,
	Rick Chen <rick@andestech.com>, "Simon Glass" <sjg@chromium.org>,
	<u-boot@lists.denx.de>
Subject: Re: [RFC PATCH] riscv: cpu: check U-Mode before counteren write
Date: Wed, 1 Feb 2023 06:52:29 +0000	[thread overview]
Message-ID: <Y9oMLXp9FdyR7hMD@ubuntu01> (raw)
In-Reply-To: <20221214055843.7177-1-nikita.shubin@maquefel.me>

On Wed, Dec 14, 2022 at 08:58:43AM +0300, Nikita Shubin wrote:
> From: Nikita Shubin <n.shubin@yadro.com>
> 
> The Priv ISA states:
> "In systems without U-mode, the mcounteren register should
> not exist."
> 
> Check U-Mode is present in MISA before writing to counteren, otherwise
> we endup with Illegal Instruction exception on systems without U-Mode.
> 
> Also make checking MISA default for M-Mode.
> 
> Signed-off-by: Nikita Shubin <n.shubin@yadro.com>
> ---
> This seems obvious at first glance, but i've never seen 'u' extension 
> enywhere in "riscv,isa" device tree property, even qemu doesn't set this, 
> and if we simply enable this check - this will break existing board for sure.
> 
> We can rely on MISA completely if we are in M-Mode, as we currently check only
> 'd', 'f' and 'u', which are standart and nothing fancy.
> ---
>  arch/riscv/cpu/cpu.c | 16 ++++++++--------
>  1 file changed, 8 insertions(+), 8 deletions(-)
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>

      reply	other threads:[~2023-02-01  6:52 UTC|newest]

Thread overview: 2+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-12-14  5:58 [RFC PATCH] riscv: cpu: check U-Mode before counteren write Nikita Shubin
2023-02-01  6:52 ` Leo Liang [this message]

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