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Mon, 18 Jan 2021 07:53:55 -0500 (EST) Date: Mon, 18 Jan 2021 13:53:53 +0100 From: Klaus Jensen To: Minwoo Im Subject: Re: [PATCH v2 02/12] hw/block/nvme: fix 64 bit register hi/lo split writes Message-ID: References: <20210118094705.56772-1-its@irrelevant.dk> <20210118094705.56772-3-its@irrelevant.dk> <20210118124100.GB18718@localhost.localdomain> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="0bZi2fgMGVYlTvNP" Content-Disposition: inline In-Reply-To: <20210118124100.GB18718@localhost.localdomain> Received-SPF: pass client-ip=66.111.4.25; envelope-from=its@irrelevant.dk; helo=out1-smtp.messagingengine.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Fam Zheng , Kevin Wolf , qemu-block@nongnu.org, Klaus Jensen , qemu-devel@nongnu.org, Max Reitz , Stefan Hajnoczi , Keith Busch Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" --0bZi2fgMGVYlTvNP Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Jan 18 21:41, Minwoo Im wrote: > On 21-01-18 10:46:55, Klaus Jensen wrote: > > From: Klaus Jensen > >=20 > > 64 bit registers like ASQ and ACQ should be writable by both a hi/lo 32 > > bit write combination as well as a plain 64 bit write. The spec does not > > define ordering on the hi/lo split, but the code currently assumes that > > the low order bits are written first. Additionally, the code does not > > consider that another address might already have been written into the > > register, causing the OR'ing to result in a bad address. > >=20 > > Fix this by explicitly overwriting only the low or high order bits for > > 32 bit writes. > >=20 > > Signed-off-by: Klaus Jensen > > --- > > hw/block/nvme.c | 10 ++++++---- > > 1 file changed, 6 insertions(+), 4 deletions(-) > >=20 > > diff --git a/hw/block/nvme.c b/hw/block/nvme.c > > index bd7e258c3c26..40b9f8ccfc0e 100644 > > --- a/hw/block/nvme.c > > +++ b/hw/block/nvme.c > > @@ -3781,19 +3781,21 @@ static void nvme_write_bar(NvmeCtrl *n, hwaddr = offset, uint64_t data, > > trace_pci_nvme_mmio_aqattr(data & 0xffffffff); > > break; > > case 0x28: /* ASQ */ > > - n->bar.asq =3D data; > > + n->bar.asq =3D size =3D=3D 8 ? data : > > + (n->bar.asq & ~0xffffffff) | (data & 0xffffffff); > ^^^^^^^^^^^ > If this one is to unmask lower 32bits other than higher 32bits, then > it should be: >=20 > (n->bar.asq & ~0xffffffffULL) >=20 Ouch. Yes, thanks! > Also, maybe we should take care of lower than 4bytes as: >=20 > .min_access_size =3D 2, > .max_access_size =3D 8, >=20 > Even we have some error messages up there with: >=20 > if (unlikely(size < sizeof(uint32_t))) { > NVME_GUEST_ERR(pci_nvme_ub_mmiowr_toosmall, > "MMIO write smaller than 32-bits," > " offset=3D0x%"PRIx64", size=3D%u", > offset, size); > /* should be ignored, fall through for now */ > } >=20 > It's a fall-thru error, and that's it. I would prefer not to have this > error and support for 2bytes access also, OR do not support for 2bytes > access for this MMIO area. >=20 The spec requires aligned 32 bit accesses (or the size of the register), so maybe it's about time we actually ignore instead of falling through. --0bZi2fgMGVYlTvNP Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- iQEzBAEBCAAdFiEEUigzqnXi3OaiR2bATeGvMW1PDekFAmAFhN4ACgkQTeGvMW1P DenSagf9Fr2EsBhCFR1eaieGl5sF4iF/PzRP4gV0/wDuu8sqS0J4tUHbA+OWBWXT sAUDzNBqosH9Gr2DDdH6qGdba+tOGET+UskidgLt+DVnlue/Eg/pDyQt2EzCG/GK xufAZXLfS/h3N0R167qKGfTrb5r6dqA+Lnp2Slt1gPXwNEhcdPsKQa2X535e+zZl wDadGY2qyPHMbEd1xh1Me5YB1UkEe7LlbA+DynXWvmCE0HFy2E5bUmOBn4YxvdRm Pvp0ZFahK53qNuY8rBDAbZLjC8dcUDIXnK+IICgiEx1GjQcjOKeOHmJs/IlWe2yZ 24MTNwrZb3nvsnpx5Axg7JrDZvdOVA== =bW0q -----END PGP SIGNATURE----- --0bZi2fgMGVYlTvNP--