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From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: Imre Deak <imre.deak@intel.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH 4/5] drm/i915: Move HDMI vswing programming to the right place
Date: Fri, 29 Jan 2021 19:32:51 +0200	[thread overview]
Message-ID: <YBRGw2JV7lucuBEC@intel.com> (raw)
In-Reply-To: <20210129172249.GD183052@ideak-desk.fi.intel.com>

On Fri, Jan 29, 2021 at 07:22:49PM +0200, Imre Deak wrote:
> On Thu, Jan 28, 2021 at 05:59:47PM +0200, Ville Syrjala wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > 
> > The documented programming sequence indicates the correct point
> > for the vswing programming is just before we enable the DDI.
> > Make it so.
> > 
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/intel_ddi.c | 30 ++++++++++++------------
> >  1 file changed, 15 insertions(+), 15 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> > index 8fbeb8c24efb..efcdf5499903 100644
> > --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> > @@ -3893,7 +3893,6 @@ static void intel_ddi_pre_enable_hdmi(struct intel_atomic_state *state,
> >  	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
> >  	struct intel_hdmi *intel_hdmi = &dig_port->hdmi;
> >  	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> > -	int level = intel_ddi_hdmi_level(encoder, crtc_state);
> >  
> >  	intel_dp_dual_mode_set_tmds_output(intel_hdmi, true);
> >  	intel_ddi_clk_select(encoder, crtc_state);
> > @@ -3904,20 +3903,6 @@ static void intel_ddi_pre_enable_hdmi(struct intel_atomic_state *state,
> >  
> >  	icl_program_mg_dp_mode(dig_port, crtc_state);
> >  
> > -	if (INTEL_GEN(dev_priv) >= 12)
> > -		tgl_ddi_vswing_sequence(encoder, crtc_state, level);
> > -	else if (INTEL_GEN(dev_priv) == 11)
> > -		icl_ddi_vswing_sequence(encoder, crtc_state, level);
> > -	else if (IS_CANNONLAKE(dev_priv))
> > -		cnl_ddi_vswing_sequence(encoder, crtc_state, level);
> > -	else if (IS_GEN9_LP(dev_priv))
> > -		bxt_ddi_vswing_sequence(encoder, crtc_state, level);
> > -	else
> > -		intel_prepare_hdmi_ddi_buffers(encoder, level);
> > -
> > -	if (IS_GEN9_BC(dev_priv))
> > -		skl_ddi_set_iboost(encoder, crtc_state, level);
> > -
> >  	intel_ddi_enable_pipe_clock(encoder, crtc_state);
> >  
> >  	dig_port->set_infoframes(encoder,
> > @@ -4293,6 +4278,7 @@ static void intel_enable_ddi_hdmi(struct intel_atomic_state *state,
> >  	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> >  	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
> >  	struct drm_connector *connector = conn_state->connector;
> > +	int level = intel_ddi_hdmi_level(encoder, crtc_state);
> >  	enum port port = encoder->port;
> >  
> >  	if (!intel_hdmi_handle_sink_scrambling(encoder, connector,
> > @@ -4302,6 +4288,20 @@ static void intel_enable_ddi_hdmi(struct intel_atomic_state *state,
> >  			    "[CONNECTOR:%d:%s] Failed to configure sink scrambling/TMDS bit clock ratio\n",
> >  			    connector->base.id, connector->name);
> >  
> > +	if (INTEL_GEN(dev_priv) >= 12)
> > +		tgl_ddi_vswing_sequence(encoder, crtc_state, level);
> > +	else if (INTEL_GEN(dev_priv) == 11)
> > +		icl_ddi_vswing_sequence(encoder, crtc_state, level);
> > +	else if (IS_CANNONLAKE(dev_priv))
> > +		cnl_ddi_vswing_sequence(encoder, crtc_state, level);
> > +	else if (IS_GEN9_LP(dev_priv))
> > +		bxt_ddi_vswing_sequence(encoder, crtc_state, level);
> > +	else
> > +		intel_prepare_hdmi_ddi_buffers(encoder, level);
> 
> It's not specified where to do this on HSW, but I assume it matches BDW:

Should be fine. All we get on HSW is
"DDI_BUF_TRANS: ...
 Restriction : These registers must be programmed with valid values
 prior to enabling DDI_BUF_CTL."

> Reviewed-by: Imre Deak <imre.deak@intel.com>
> 
> > +
> > +	if (IS_GEN9_BC(dev_priv))
> > +		skl_ddi_set_iboost(encoder, crtc_state, level);
> > +
> >  	/* Display WA #1143: skl,kbl,cfl */
> >  	if (IS_GEN9_BC(dev_priv)) {
> >  		/*
> > -- 
> > 2.26.2
> > 
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

  reply	other threads:[~2021-01-29 17:32 UTC|newest]

Thread overview: 24+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-01-28 15:59 [Intel-gfx] [PATCH 1/5] drm/i915: Skip vswing programming for TBT Ville Syrjala
2021-01-28 15:59 ` Ville Syrjala
2021-01-28 15:59 ` [Intel-gfx] [PATCH 2/5] drm/i915: Extract intel_ddi_power_up_lanes() Ville Syrjala
2021-01-28 15:59   ` Ville Syrjala
2021-01-29 16:57   ` [Intel-gfx] " Imre Deak
2021-01-29 16:57     ` Imre Deak
2021-01-28 15:59 ` [Intel-gfx] [PATCH 3/5] drm/i915: Power up combo PHY lanes for for HDMI as well Ville Syrjala
2021-01-28 15:59   ` Ville Syrjala
2021-01-29 17:06   ` [Intel-gfx] " Imre Deak
2021-01-29 17:06     ` Imre Deak
2021-01-29 17:18     ` Ville Syrjälä
2021-01-29 17:18       ` Ville Syrjälä
2021-01-29 17:40       ` Imre Deak
2021-01-29 17:40         ` Imre Deak
2021-01-28 15:59 ` [Intel-gfx] [PATCH 4/5] drm/i915: Move HDMI vswing programming to the right place Ville Syrjala
2021-01-29 17:22   ` Imre Deak
2021-01-29 17:32     ` Ville Syrjälä [this message]
2021-01-28 15:59 ` [Intel-gfx] [PATCH 5/5] drm/i915: Don't check tc_mode unless dealing with a TC PHY Ville Syrjala
2021-01-29 17:23   ` Imre Deak
2021-01-28 16:41 ` [Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [1/5] drm/i915: Skip vswing programming for TBT Patchwork
2021-01-28 19:26 ` [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/5] drm/i915: Skip vswing programming for TBT (rev2) Patchwork
2021-01-29 11:25 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
2021-01-29 16:56 ` [Intel-gfx] [PATCH 1/5] drm/i915: Skip vswing programming for TBT Imre Deak
2021-01-29 16:56   ` Imre Deak

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