All of lore.kernel.org
 help / color / mirror / Atom feed
From: "Roger Pau Monné" <roger.pau@citrix.com>
To: Andrew Cooper <andrew.cooper3@citrix.com>
Cc: Jan Beulich <jbeulich@suse.com>,
	"xen-devel@lists.xenproject.org" <xen-devel@lists.xenproject.org>,
	Wei Liu <wl@xen.org>, Ian Jackson <iwj@xenproject.org>
Subject: Re: [PATCH v2 2/2][4.15] x86/AMD: expose HWCR.TscFreqSel to guests
Date: Mon, 8 Mar 2021 14:23:25 +0100	[thread overview]
Message-ID: <YEYlTSkm5jmP2qeE@Air-de-Roger> (raw)
In-Reply-To: <d4e927da-97ee-d4ca-2407-03793f2f4c24@citrix.com>

On Mon, Mar 08, 2021 at 12:41:26PM +0000, Andrew Cooper wrote:
> On 05/03/2021 09:50, Jan Beulich wrote:
> > Linux has been warning ("firmware bug") about this bit being clear for a
> > long time. While writable in older hardware it has been readonly on more
> > than just most recent hardware. For simplicitly report it always set (if
> > anything we may want to log the issue ourselves if it turns out to be
> > clear on older hardware).
> >
> > Signed-off-by: Jan Beulich <jbeulich@suse.com>
> 
> I realise Linux is complaining, but simply setting the bit isn't a fix.
> 
> This needs corresponding updates in the ACPI tables, as well as Pstate
> MSRs, or Linux will derive a false relationship between the TSC rate and
> wallclock.

Is there any description of those relations?

I don't seem to find any other MSR referencing the TscFreqSel bit in
HWCR on the AMD Open-Source Register Reference, but I might be looking
at the wrong place.

Thanks, Roger.


  reply	other threads:[~2021-03-08 13:24 UTC|newest]

Thread overview: 20+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-03-05  9:43 [PATCH v2 0/2][4.15] x86: guest MSR access handling tweaks Jan Beulich
2021-03-05  9:50 ` [PATCH v2 1/2][4.15] x86/PV: conditionally avoid raising #GP for early guest MSR reads Jan Beulich
2021-03-08  8:56   ` Roger Pau Monné
2021-03-08  9:33     ` Jan Beulich
2021-03-08 12:11       ` Roger Pau Monné
2021-03-08 13:49         ` Jan Beulich
2021-03-09 10:17           ` Roger Pau Monné
2021-03-09 11:16             ` Jan Beulich
2021-03-09 13:37               ` Roger Pau Monné
2021-03-09 14:50                 ` Jan Beulich
2021-03-09 15:19                   ` Roger Pau Monné
2021-03-09 16:07                     ` Jan Beulich
2021-03-05  9:50 ` [PATCH v2 2/2][4.15] x86/AMD: expose HWCR.TscFreqSel to guests Jan Beulich
2021-03-08 11:37   ` Roger Pau Monné
2021-03-08 11:47     ` Jan Beulich
2021-03-08 12:29       ` Roger Pau Monné
2021-03-08 13:42         ` Jan Beulich
2021-03-08 12:41   ` Andrew Cooper
2021-03-08 13:23     ` Roger Pau Monné [this message]
2021-03-08 13:24     ` Jan Beulich

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=YEYlTSkm5jmP2qeE@Air-de-Roger \
    --to=roger.pau@citrix.com \
    --cc=andrew.cooper3@citrix.com \
    --cc=iwj@xenproject.org \
    --cc=jbeulich@suse.com \
    --cc=wl@xen.org \
    --cc=xen-devel@lists.xenproject.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body. 
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.