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From: Andrew Lunn <andrew@lunn.ch>
To: Robert Hancock <robert.hancock@calian.com>
Cc: davem@davemloft.net, kuba@kernel.org,
	radhey.shyam.pandey@xilinx.com, robh@kernel.org,
	devicetree@vger.kernel.org, netdev@vger.kernel.org
Subject: Re: [PATCH net-next v4 2/2] net: axienet: Enable more clocks
Date: Fri, 26 Mar 2021 13:14:48 +0100	[thread overview]
Message-ID: <YF3QOFw7jREj03Ut@lunn.ch> (raw)
In-Reply-To: <20210326000438.2292548-3-robert.hancock@calian.com>

On Thu, Mar 25, 2021 at 06:04:38PM -0600, Robert Hancock wrote:
> This driver was only enabling the first clock on the device, regardless
> of its name. However, this controller logic can have multiple clocks
> which should all be enabled. Add support for enabling additional clocks.
> The clock names used are matching those used in the Xilinx version of this
> driver as well as the Xilinx device tree generator, except for mgt_clk
> which is not present there.
> 
> For backward compatibility, if no named clocks are present, the first
> clock present is used for determining the MDIO bus clock divider.
> 
> Reviewed-by: Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com>
> Signed-off-by: Robert Hancock <robert.hancock@calian.com>

Reviewed-by: Andrew Lunn <andrew@lunn.ch>

    Andrew

  reply	other threads:[~2021-03-26 12:15 UTC|newest]

Thread overview: 6+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-03-26  0:04 [PATCH net-next v4 0/2] axienet clock additions Robert Hancock
2021-03-26  0:04 ` [PATCH net-next v4 1/2] dt-bindings: net: xilinx_axienet: Document additional clocks Robert Hancock
2021-03-26 12:12   ` Andrew Lunn
2021-03-26  0:04 ` [PATCH net-next v4 2/2] net: axienet: Enable more clocks Robert Hancock
2021-03-26 12:14   ` Andrew Lunn [this message]
2021-03-26 23:00 ` [PATCH net-next v4 0/2] axienet clock additions patchwork-bot+netdevbpf

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