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[35.233.69.230]) by smtp.gmail.com with ESMTPSA id a8sm2679076wmm.46.2021.03.17.07.51.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 Mar 2021 07:51:37 -0700 (PDT) Date: Wed, 17 Mar 2021 14:51:34 +0000 From: Quentin Perret To: Will Deacon Subject: Re: [PATCH 1/2] KVM: arm64: Introduce KVM_PGTABLE_S2_NOFWB Stage-2 flag Message-ID: References: <20210315143536.214621-34-qperret@google.com> <20210317141714.383046-1-qperret@google.com> <20210317141714.383046-2-qperret@google.com> <20210317144246.GE5393@willie-the-truck> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20210317144246.GE5393@willie-the-truck> Cc: android-kvm@google.com, catalin.marinas@arm.com, mate.toth-pal@arm.com, seanjc@google.com, tabba@google.com, linux-kernel@vger.kernel.org, robh+dt@kernel.org, linux-arm-kernel@lists.infradead.org, maz@kernel.org, kernel-team@android.com, kvmarm@lists.cs.columbia.edu X-BeenThere: kvmarm@lists.cs.columbia.edu X-Mailman-Version: 2.1.14 Precedence: list List-Id: Where KVM/ARM decisions are made List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Errors-To: kvmarm-bounces@lists.cs.columbia.edu Sender: kvmarm-bounces@lists.cs.columbia.edu On Wednesday 17 Mar 2021 at 14:42:46 (+0000), Will Deacon wrote: > On Wed, Mar 17, 2021 at 02:17:13PM +0000, Quentin Perret wrote: > > In order to further configure stage-2 page-tables, pass flags to the > > init function using a new enum. > > > > The first of these flags allows to disable FWB even if the hardware > > supports it as we will need to do so for the host stage-2. > > > > Signed-off-by: Quentin Perret > > > > --- > > > > One question is, do we want to use stage2_has_fwb() everywhere, including > > guest-specific paths (e.g. kvm_arch_prepare_memory_region(), ...) ? > > > > That'd make this patch more intrusive, but would make the whole codebase > > work with FWB enabled on a guest by guest basis. I don't see us use that > > anytime soon (other than maybe debug of some sort?) but it'd be good to > > have an agreement. > > I don't see the value in spreading this everywhere for now. Good. Sounds like we're all in agreement. > > arch/arm64/include/asm/kvm_pgtable.h | 19 +++++++++-- > > arch/arm64/include/asm/pgtable-prot.h | 4 +-- > > arch/arm64/kvm/hyp/pgtable.c | 49 +++++++++++++++++---------- > > 3 files changed, 50 insertions(+), 22 deletions(-) > > > > diff --git a/arch/arm64/include/asm/kvm_pgtable.h b/arch/arm64/include/asm/kvm_pgtable.h > > index b93a2a3526ab..7382bdfb6284 100644 > > --- a/arch/arm64/include/asm/kvm_pgtable.h > > +++ b/arch/arm64/include/asm/kvm_pgtable.h > > @@ -56,6 +56,15 @@ struct kvm_pgtable_mm_ops { > > phys_addr_t (*virt_to_phys)(void *addr); > > }; > > > > +/** > > + * enum kvm_pgtable_stage2_flags - Stage-2 page-table flags. > > + * @KVM_PGTABLE_S2_NOFWB: Don't enforce Normal-WB even if the CPUs have > > + * ARM64_HAS_STAGE2_FWB. > > + */ > > +enum kvm_pgtable_stage2_flags { > > + KVM_PGTABLE_S2_NOFWB = BIT(0), > > +}; > > + > > /** > > * struct kvm_pgtable - KVM page-table. > > * @ia_bits: Maximum input address size, in bits. > > @@ -72,6 +81,7 @@ struct kvm_pgtable { > > > > /* Stage-2 only */ > > struct kvm_s2_mmu *mmu; > > + enum kvm_pgtable_stage2_flags flags; > > }; > > > > /** > > @@ -201,11 +211,16 @@ u64 kvm_get_vtcr(u64 mmfr0, u64 mmfr1, u32 phys_shift); > > * @arch: Arch-specific KVM structure representing the guest virtual > > * machine. > > * @mm_ops: Memory management callbacks. > > + * @flags: Stage-2 configuration flags. > > * > > * Return: 0 on success, negative error code on failure. > > */ > > -int kvm_pgtable_stage2_init(struct kvm_pgtable *pgt, struct kvm_arch *arch, > > - struct kvm_pgtable_mm_ops *mm_ops); > > +int kvm_pgtable_stage2_init_flags(struct kvm_pgtable *pgt, struct kvm_arch *arch, > > + struct kvm_pgtable_mm_ops *mm_ops, > > + enum kvm_pgtable_stage2_flags flags); > > + > > +#define kvm_pgtable_stage2_init(pgt, arch, mm_ops) \ > > + kvm_pgtable_stage2_init_flags(pgt, arch, mm_ops, 0) > > nit: I think some of the kerneldoc refers to "kvm_pgtable_stage_init()" > so that needs a trivial update to e.g. "kvm_pgtable_stage_init*()". Will do. > > diff --git a/arch/arm64/include/asm/pgtable-prot.h b/arch/arm64/include/asm/pgtable-prot.h > > index 046be789fbb4..beeb722a82d3 100644 > > --- a/arch/arm64/include/asm/pgtable-prot.h > > +++ b/arch/arm64/include/asm/pgtable-prot.h > > @@ -72,10 +72,10 @@ extern bool arm64_use_ng_mappings; > > #define PAGE_KERNEL_EXEC __pgprot(PROT_NORMAL & ~PTE_PXN) > > #define PAGE_KERNEL_EXEC_CONT __pgprot((PROT_NORMAL & ~PTE_PXN) | PTE_CONT) > > > > -#define PAGE_S2_MEMATTR(attr) \ > > +#define PAGE_S2_MEMATTR(attr, has_fwb) \ > > ({ \ > > u64 __val; \ > > - if (cpus_have_const_cap(ARM64_HAS_STAGE2_FWB)) \ > > + if (has_fwb) \ > > __val = PTE_S2_MEMATTR(MT_S2_FWB_ ## attr); \ > > else \ > > __val = PTE_S2_MEMATTR(MT_S2_ ## attr); \ > > Can you take the pgt structure instead of a bool here, or does it end up > being really ugly? It means I need to expose the stage2_has_fwb() helper in pgtable.h so I can use it here. But Marc suggested that I introduce another macro along the lines of #define KVM_S2_MEMATTR(pgt, attr) PAGE_S2_MEMATTR(attr, stage2_has_fwb(pgt)) which can be defined in pgtable.c and keep everything neatly contained in there. So I think I'll go ahead with that unless you feel strongly about it. Cheers, Quentin _______________________________________________ kvmarm mailing list kvmarm@lists.cs.columbia.edu https://lists.cs.columbia.edu/mailman/listinfo/kvmarm From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-14.0 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_ADSP_CUSTOM_MED,DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 32C38C433E6 for ; Wed, 17 Mar 2021 14:54:07 +0000 (UTC) Received: from desiato.infradead.org (desiato.infradead.org [90.155.92.199]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 5EEC764F3E for ; Wed, 17 Mar 2021 14:54:06 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 5EEC764F3E Authentication-Results: mail.kernel.org; dmarc=fail (p=reject dis=none) header.from=google.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=desiato.20200630; h=Sender:Content-Transfer-Encoding :Content-Type:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References:Message-ID: Subject:Cc:To:From:Date:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=FjCDY0CKlDYrdHXK5uZg30LnoEWnlTLgfl+JKL4Ep1E=; b=bJuq0CKzPoIOYMjhzZYieNdq2 sxVOdpFVmiSA6prYzogy+OHOh5oDkO6KHh4f82vlpP936MgaBWtgYQydYd0qFfBFMJbQX4mmH7VIE C+9drz8jtaJqCETV9zh3hAFTdQFcb9mrTnJ9odacR6n3mRu4N0jOyjy8eKYEhohH2nWfFBSNFBerW TC9szxP/lCCcGf39Y0lbqx3puSxQ0uOseh/TUyRyzuTFXisSlEayVjv6yU1W2bd/DQaYvIVQZ48/C eX7FyIEvhhCHpXwhqdchaseJKPoBiw6aLqM0kRROrKb6R16rjZIhNL8JJjv7TtO+oG5+0s9t6R6nJ hLB45KSiA==; Received: from localhost ([::1] helo=desiato.infradead.org) by desiato.infradead.org with esmtp (Exim 4.94 #2 (Red Hat Linux)) id 1lMXWr-003N08-Uu; Wed, 17 Mar 2021 14:52:10 +0000 Received: from mail-wr1-x429.google.com ([2a00:1450:4864:20::429]) by desiato.infradead.org with esmtps (Exim 4.94 #2 (Red Hat Linux)) id 1lMXWM-003MtV-IJ for linux-arm-kernel@lists.infradead.org; Wed, 17 Mar 2021 14:51:41 +0000 Received: by mail-wr1-x429.google.com with SMTP id z2so2116111wrl.5 for ; Wed, 17 Mar 2021 07:51:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20161025; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to; bh=2QJmRsVKTO5ci+HipbAp9Ce4exjAggLbAvM7AZ2sv2M=; b=GQhXWmat7a3XTiXnO9GkRqto6Und9lUPumlzu/jUj0TT933/hJv0wAQBjr5KdA1yRH W9zqwp2AdQZVkO/IKoeGlp5fgOGbG+ZqR8pVp0hyQK3uRldI2qI/lE/DESIclnfQYNEa qNHr6DBBi6WT9s8ZL8ccUUnZ1dosNmMAWQZ02Vg6uyS5yndjxIZM3F+OKDNi1xXkUkiE JaQkqStzEtvwyuC2pQr2mCRB6yQuKFGvSeb1bGeOAOLO+rhqiYWgQlqQi0e1Zt2MhsXu 9VSfO+dHRMSrQkM9SvMFEhwIIC1LESpUzEJgNJhe5sRTorXxYQ0f0PcHrrqVSiFXNS1E RkPA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to; bh=2QJmRsVKTO5ci+HipbAp9Ce4exjAggLbAvM7AZ2sv2M=; b=a7jftUJk/f5QJOXSo/C92VkyMcOfCJf9EXi5HZ7GxhgftM6jBBpOvSAFOIeMKjk/S0 kg4oWKHajWg+YcnOxP7kfO/TjmqbksfiDqGFr/Y1Rw+dOgsTihyo25E5e0oVFW+cpuMZ k3BvsRkx24mIxcXFAQ+VJi36d66eodmbVI4KfgbbSU+Nr8f6gYpfDcC/sD3NOQ1sWsQu 9KZvbqFWVKoivy1tcpBppUkEytH6p9yo1rF/EiZYukXRVLMnTjupWrnS4b2oLMFidZAS Ew+5HwnYAHFQPFJ++IxfsEoLB/YFP3KhfNQX9p66MlW/R4gE/LHK65sdFH64R4mSig1Y +rGQ== X-Gm-Message-State: AOAM532gszNHXX9l2mTe7ZPI+2kiXaBrHAEnUQ/fjqtic8h5QQLLrL9e IvlRURmKWvMtYZpL2YafxSRYOQ== X-Google-Smtp-Source: ABdhPJzU4mf1HgHLDhfex0ruEOsnW2Z8/qwymFAQXQiSoFpEMKwn6XWMuH5WHfLKOiAPW0wNje1c4Q== X-Received: by 2002:adf:e582:: with SMTP id l2mr4833991wrm.207.1615992697694; Wed, 17 Mar 2021 07:51:37 -0700 (PDT) Received: from google.com (230.69.233.35.bc.googleusercontent.com. [35.233.69.230]) by smtp.gmail.com with ESMTPSA id a8sm2679076wmm.46.2021.03.17.07.51.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 Mar 2021 07:51:37 -0700 (PDT) Date: Wed, 17 Mar 2021 14:51:34 +0000 From: Quentin Perret To: Will Deacon Cc: catalin.marinas@arm.com, maz@kernel.org, james.morse@arm.com, julien.thierry.kdev@gmail.com, suzuki.poulose@arm.com, android-kvm@google.com, seanjc@google.com, linux-kernel@vger.kernel.org, robh+dt@kernel.org, linux-arm-kernel@lists.infradead.org, kernel-team@android.com, kvmarm@lists.cs.columbia.edu, tabba@google.com, ardb@kernel.org, mark.rutland@arm.com, dbrazdil@google.com, mate.toth-pal@arm.com Subject: Re: [PATCH 1/2] KVM: arm64: Introduce KVM_PGTABLE_S2_NOFWB Stage-2 flag Message-ID: References: <20210315143536.214621-34-qperret@google.com> <20210317141714.383046-1-qperret@google.com> <20210317141714.383046-2-qperret@google.com> <20210317144246.GE5393@willie-the-truck> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20210317144246.GE5393@willie-the-truck> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210317_145139_121777_9CE6F6E7 X-CRM114-Status: GOOD ( 32.76 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Wednesday 17 Mar 2021 at 14:42:46 (+0000), Will Deacon wrote: > On Wed, Mar 17, 2021 at 02:17:13PM +0000, Quentin Perret wrote: > > In order to further configure stage-2 page-tables, pass flags to the > > init function using a new enum. > > > > The first of these flags allows to disable FWB even if the hardware > > supports it as we will need to do so for the host stage-2. > > > > Signed-off-by: Quentin Perret > > > > --- > > > > One question is, do we want to use stage2_has_fwb() everywhere, including > > guest-specific paths (e.g. kvm_arch_prepare_memory_region(), ...) ? > > > > That'd make this patch more intrusive, but would make the whole codebase > > work with FWB enabled on a guest by guest basis. I don't see us use that > > anytime soon (other than maybe debug of some sort?) but it'd be good to > > have an agreement. > > I don't see the value in spreading this everywhere for now. Good. Sounds like we're all in agreement. > > arch/arm64/include/asm/kvm_pgtable.h | 19 +++++++++-- > > arch/arm64/include/asm/pgtable-prot.h | 4 +-- > > arch/arm64/kvm/hyp/pgtable.c | 49 +++++++++++++++++---------- > > 3 files changed, 50 insertions(+), 22 deletions(-) > > > > diff --git a/arch/arm64/include/asm/kvm_pgtable.h b/arch/arm64/include/asm/kvm_pgtable.h > > index b93a2a3526ab..7382bdfb6284 100644 > > --- a/arch/arm64/include/asm/kvm_pgtable.h > > +++ b/arch/arm64/include/asm/kvm_pgtable.h > > @@ -56,6 +56,15 @@ struct kvm_pgtable_mm_ops { > > phys_addr_t (*virt_to_phys)(void *addr); > > }; > > > > +/** > > + * enum kvm_pgtable_stage2_flags - Stage-2 page-table flags. > > + * @KVM_PGTABLE_S2_NOFWB: Don't enforce Normal-WB even if the CPUs have > > + * ARM64_HAS_STAGE2_FWB. > > + */ > > +enum kvm_pgtable_stage2_flags { > > + KVM_PGTABLE_S2_NOFWB = BIT(0), > > +}; > > + > > /** > > * struct kvm_pgtable - KVM page-table. > > * @ia_bits: Maximum input address size, in bits. > > @@ -72,6 +81,7 @@ struct kvm_pgtable { > > > > /* Stage-2 only */ > > struct kvm_s2_mmu *mmu; > > + enum kvm_pgtable_stage2_flags flags; > > }; > > > > /** > > @@ -201,11 +211,16 @@ u64 kvm_get_vtcr(u64 mmfr0, u64 mmfr1, u32 phys_shift); > > * @arch: Arch-specific KVM structure representing the guest virtual > > * machine. > > * @mm_ops: Memory management callbacks. > > + * @flags: Stage-2 configuration flags. > > * > > * Return: 0 on success, negative error code on failure. > > */ > > -int kvm_pgtable_stage2_init(struct kvm_pgtable *pgt, struct kvm_arch *arch, > > - struct kvm_pgtable_mm_ops *mm_ops); > > +int kvm_pgtable_stage2_init_flags(struct kvm_pgtable *pgt, struct kvm_arch *arch, > > + struct kvm_pgtable_mm_ops *mm_ops, > > + enum kvm_pgtable_stage2_flags flags); > > + > > +#define kvm_pgtable_stage2_init(pgt, arch, mm_ops) \ > > + kvm_pgtable_stage2_init_flags(pgt, arch, mm_ops, 0) > > nit: I think some of the kerneldoc refers to "kvm_pgtable_stage_init()" > so that needs a trivial update to e.g. "kvm_pgtable_stage_init*()". Will do. > > diff --git a/arch/arm64/include/asm/pgtable-prot.h b/arch/arm64/include/asm/pgtable-prot.h > > index 046be789fbb4..beeb722a82d3 100644 > > --- a/arch/arm64/include/asm/pgtable-prot.h > > +++ b/arch/arm64/include/asm/pgtable-prot.h > > @@ -72,10 +72,10 @@ extern bool arm64_use_ng_mappings; > > #define PAGE_KERNEL_EXEC __pgprot(PROT_NORMAL & ~PTE_PXN) > > #define PAGE_KERNEL_EXEC_CONT __pgprot((PROT_NORMAL & ~PTE_PXN) | PTE_CONT) > > > > -#define PAGE_S2_MEMATTR(attr) \ > > +#define PAGE_S2_MEMATTR(attr, has_fwb) \ > > ({ \ > > u64 __val; \ > > - if (cpus_have_const_cap(ARM64_HAS_STAGE2_FWB)) \ > > + if (has_fwb) \ > > __val = PTE_S2_MEMATTR(MT_S2_FWB_ ## attr); \ > > else \ > > __val = PTE_S2_MEMATTR(MT_S2_ ## attr); \ > > Can you take the pgt structure instead of a bool here, or does it end up > being really ugly? It means I need to expose the stage2_has_fwb() helper in pgtable.h so I can use it here. But Marc suggested that I introduce another macro along the lines of #define KVM_S2_MEMATTR(pgt, attr) PAGE_S2_MEMATTR(attr, stage2_has_fwb(pgt)) which can be defined in pgtable.c and keep everything neatly contained in there. So I think I'll go ahead with that unless you feel strongly about it. Cheers, Quentin _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-23.3 required=3.0 tests=BAYES_00,DKIMWL_WL_MED, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS, USER_IN_DEF_DKIM_WL autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 20128C4332E for ; Wed, 17 Mar 2021 15:53:01 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id E1A2D64F5E for ; Wed, 17 Mar 2021 15:53:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232346AbhCQPwl (ORCPT ); Wed, 17 Mar 2021 11:52:41 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44666 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232000AbhCQPwB (ORCPT ); Wed, 17 Mar 2021 11:52:01 -0400 Received: from mail-wr1-x433.google.com (mail-wr1-x433.google.com [IPv6:2a00:1450:4864:20::433]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 106B8C06174A for ; Wed, 17 Mar 2021 07:51:39 -0700 (PDT) Received: by mail-wr1-x433.google.com with SMTP id v11so2117826wro.7 for ; Wed, 17 Mar 2021 07:51:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20161025; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to; bh=2QJmRsVKTO5ci+HipbAp9Ce4exjAggLbAvM7AZ2sv2M=; b=GQhXWmat7a3XTiXnO9GkRqto6Und9lUPumlzu/jUj0TT933/hJv0wAQBjr5KdA1yRH W9zqwp2AdQZVkO/IKoeGlp5fgOGbG+ZqR8pVp0hyQK3uRldI2qI/lE/DESIclnfQYNEa qNHr6DBBi6WT9s8ZL8ccUUnZ1dosNmMAWQZ02Vg6uyS5yndjxIZM3F+OKDNi1xXkUkiE JaQkqStzEtvwyuC2pQr2mCRB6yQuKFGvSeb1bGeOAOLO+rhqiYWgQlqQi0e1Zt2MhsXu 9VSfO+dHRMSrQkM9SvMFEhwIIC1LESpUzEJgNJhe5sRTorXxYQ0f0PcHrrqVSiFXNS1E RkPA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to; bh=2QJmRsVKTO5ci+HipbAp9Ce4exjAggLbAvM7AZ2sv2M=; b=e1WvXs7hZYtmahIWq+BJSyMp6NdCi4q4PKcaAVOLzTNTOsekg3x6mwBwbc3lQnQA0W yOpZS4r//tdM9g1UkxN2Jc5fmCiZFRTNOvg0XryRH01433IEQQsdZwxys4EKtfpWCdH/ cFF0tf4o8vi3JHUeAbiCrIhQvreclmq0YJsFhBODlayESWukcyQDo/QeW34CbTIMr+iQ XjKxHM3ZInxtUjMoUAbP5E24mH+C9yrakUTzb0OZtTLjEHEGF9SiV8cDUyQcGKnm+Vnq jBljG9DcLungFM2gaQF2xw73T7NBBvAVNOuJA9IIU/WdVxDWW4UC0s3ysowE+R8kCm4W oxuA== X-Gm-Message-State: AOAM5303X0zRECspYjm7A6jimxwrI0x1cDPCBZcOnpNKYvwI2MCBsoOF x7yLMT9Z4jiSGje+JtHfYJEzmQ== X-Google-Smtp-Source: ABdhPJzU4mf1HgHLDhfex0ruEOsnW2Z8/qwymFAQXQiSoFpEMKwn6XWMuH5WHfLKOiAPW0wNje1c4Q== X-Received: by 2002:adf:e582:: with SMTP id l2mr4833991wrm.207.1615992697694; Wed, 17 Mar 2021 07:51:37 -0700 (PDT) Received: from google.com (230.69.233.35.bc.googleusercontent.com. [35.233.69.230]) by smtp.gmail.com with ESMTPSA id a8sm2679076wmm.46.2021.03.17.07.51.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 Mar 2021 07:51:37 -0700 (PDT) Date: Wed, 17 Mar 2021 14:51:34 +0000 From: Quentin Perret To: Will Deacon Cc: catalin.marinas@arm.com, maz@kernel.org, james.morse@arm.com, julien.thierry.kdev@gmail.com, suzuki.poulose@arm.com, android-kvm@google.com, seanjc@google.com, linux-kernel@vger.kernel.org, robh+dt@kernel.org, linux-arm-kernel@lists.infradead.org, kernel-team@android.com, kvmarm@lists.cs.columbia.edu, tabba@google.com, ardb@kernel.org, mark.rutland@arm.com, dbrazdil@google.com, mate.toth-pal@arm.com Subject: Re: [PATCH 1/2] KVM: arm64: Introduce KVM_PGTABLE_S2_NOFWB Stage-2 flag Message-ID: References: <20210315143536.214621-34-qperret@google.com> <20210317141714.383046-1-qperret@google.com> <20210317141714.383046-2-qperret@google.com> <20210317144246.GE5393@willie-the-truck> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20210317144246.GE5393@willie-the-truck> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wednesday 17 Mar 2021 at 14:42:46 (+0000), Will Deacon wrote: > On Wed, Mar 17, 2021 at 02:17:13PM +0000, Quentin Perret wrote: > > In order to further configure stage-2 page-tables, pass flags to the > > init function using a new enum. > > > > The first of these flags allows to disable FWB even if the hardware > > supports it as we will need to do so for the host stage-2. > > > > Signed-off-by: Quentin Perret > > > > --- > > > > One question is, do we want to use stage2_has_fwb() everywhere, including > > guest-specific paths (e.g. kvm_arch_prepare_memory_region(), ...) ? > > > > That'd make this patch more intrusive, but would make the whole codebase > > work with FWB enabled on a guest by guest basis. I don't see us use that > > anytime soon (other than maybe debug of some sort?) but it'd be good to > > have an agreement. > > I don't see the value in spreading this everywhere for now. Good. Sounds like we're all in agreement. > > arch/arm64/include/asm/kvm_pgtable.h | 19 +++++++++-- > > arch/arm64/include/asm/pgtable-prot.h | 4 +-- > > arch/arm64/kvm/hyp/pgtable.c | 49 +++++++++++++++++---------- > > 3 files changed, 50 insertions(+), 22 deletions(-) > > > > diff --git a/arch/arm64/include/asm/kvm_pgtable.h b/arch/arm64/include/asm/kvm_pgtable.h > > index b93a2a3526ab..7382bdfb6284 100644 > > --- a/arch/arm64/include/asm/kvm_pgtable.h > > +++ b/arch/arm64/include/asm/kvm_pgtable.h > > @@ -56,6 +56,15 @@ struct kvm_pgtable_mm_ops { > > phys_addr_t (*virt_to_phys)(void *addr); > > }; > > > > +/** > > + * enum kvm_pgtable_stage2_flags - Stage-2 page-table flags. > > + * @KVM_PGTABLE_S2_NOFWB: Don't enforce Normal-WB even if the CPUs have > > + * ARM64_HAS_STAGE2_FWB. > > + */ > > +enum kvm_pgtable_stage2_flags { > > + KVM_PGTABLE_S2_NOFWB = BIT(0), > > +}; > > + > > /** > > * struct kvm_pgtable - KVM page-table. > > * @ia_bits: Maximum input address size, in bits. > > @@ -72,6 +81,7 @@ struct kvm_pgtable { > > > > /* Stage-2 only */ > > struct kvm_s2_mmu *mmu; > > + enum kvm_pgtable_stage2_flags flags; > > }; > > > > /** > > @@ -201,11 +211,16 @@ u64 kvm_get_vtcr(u64 mmfr0, u64 mmfr1, u32 phys_shift); > > * @arch: Arch-specific KVM structure representing the guest virtual > > * machine. > > * @mm_ops: Memory management callbacks. > > + * @flags: Stage-2 configuration flags. > > * > > * Return: 0 on success, negative error code on failure. > > */ > > -int kvm_pgtable_stage2_init(struct kvm_pgtable *pgt, struct kvm_arch *arch, > > - struct kvm_pgtable_mm_ops *mm_ops); > > +int kvm_pgtable_stage2_init_flags(struct kvm_pgtable *pgt, struct kvm_arch *arch, > > + struct kvm_pgtable_mm_ops *mm_ops, > > + enum kvm_pgtable_stage2_flags flags); > > + > > +#define kvm_pgtable_stage2_init(pgt, arch, mm_ops) \ > > + kvm_pgtable_stage2_init_flags(pgt, arch, mm_ops, 0) > > nit: I think some of the kerneldoc refers to "kvm_pgtable_stage_init()" > so that needs a trivial update to e.g. "kvm_pgtable_stage_init*()". Will do. > > diff --git a/arch/arm64/include/asm/pgtable-prot.h b/arch/arm64/include/asm/pgtable-prot.h > > index 046be789fbb4..beeb722a82d3 100644 > > --- a/arch/arm64/include/asm/pgtable-prot.h > > +++ b/arch/arm64/include/asm/pgtable-prot.h > > @@ -72,10 +72,10 @@ extern bool arm64_use_ng_mappings; > > #define PAGE_KERNEL_EXEC __pgprot(PROT_NORMAL & ~PTE_PXN) > > #define PAGE_KERNEL_EXEC_CONT __pgprot((PROT_NORMAL & ~PTE_PXN) | PTE_CONT) > > > > -#define PAGE_S2_MEMATTR(attr) \ > > +#define PAGE_S2_MEMATTR(attr, has_fwb) \ > > ({ \ > > u64 __val; \ > > - if (cpus_have_const_cap(ARM64_HAS_STAGE2_FWB)) \ > > + if (has_fwb) \ > > __val = PTE_S2_MEMATTR(MT_S2_FWB_ ## attr); \ > > else \ > > __val = PTE_S2_MEMATTR(MT_S2_ ## attr); \ > > Can you take the pgt structure instead of a bool here, or does it end up > being really ugly? It means I need to expose the stage2_has_fwb() helper in pgtable.h so I can use it here. But Marc suggested that I introduce another macro along the lines of #define KVM_S2_MEMATTR(pgt, attr) PAGE_S2_MEMATTR(attr, stage2_has_fwb(pgt)) which can be defined in pgtable.c and keep everything neatly contained in there. So I think I'll go ahead with that unless you feel strongly about it. Cheers, Quentin