From: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
To: Catalin Marinas <catalin.marinas@arm.com>
Cc: stable@vger.kernel.org, Will Deacon <will@kernel.org>,
Vincenzo Frascino <vincenzo.frascino@arm.com>,
Mark Rutland <mark.rutland@arm.com>
Subject: Re: [PATCH stable 5.10.x] arm64: mte: Ensure TIF_MTE_ASYNC_FAULT is set atomically
Date: Mon, 19 Apr 2021 14:01:21 +0200 [thread overview]
Message-ID: <YH1xER3D4Ly+fAWQ@kroah.com> (raw)
In-Reply-To: <20210419102849.2526-1-catalin.marinas@arm.com>
On Mon, Apr 19, 2021 at 11:28:49AM +0100, Catalin Marinas wrote:
> commit 2decad92f4731fac9755a083fcfefa66edb7d67d upstream.
>
> The entry from EL0 code checks the TFSRE0_EL1 register for any
> asynchronous tag check faults in user space and sets the
> TIF_MTE_ASYNC_FAULT flag. This is not done atomically, potentially
> racing with another CPU calling set_tsk_thread_flag().
>
> Replace the non-atomic ORR+STR with an STSET instruction. While STSET
> requires ARMv8.1 and an assembler that understands LSE atomics, the MTE
> feature is part of ARMv8.5 and already requires an updated assembler.
>
> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
> Fixes: 637ec831ea4f ("arm64: mte: Handle synchronous and asynchronous tag check faults")
> Cc: <stable@vger.kernel.org> # 5.10.x
Thanks, now queued up.
greg k-h
prev parent reply other threads:[~2021-04-19 12:01 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-04-19 10:28 [PATCH stable 5.10.x] arm64: mte: Ensure TIF_MTE_ASYNC_FAULT is set atomically Catalin Marinas
2021-04-19 12:01 ` Greg Kroah-Hartman [this message]
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