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Fri, 14 May 2021 11:22:35 +0000 Received: by mail.kernel.org (Postfix) with ESMTPSA id 8B792613DE; Fri, 14 May 2021 11:22:32 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=linuxfoundation.org; s=korg; t=1620991353; bh=fdI4/WvFxLdOxw3z0CJfS4djdEHMKXDEj+klVKAPPdM=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=SfyuVtLk6E8Z65FAVs45sn4bhQlv74lXiwqfQ10FIfAcIv1uWX2qGOKNlzuX37A0V y8y/OzI4Z9TSvvbflhG9P0FK016w73qiejkBEIFf48S3YnGTV4owY+RRD7xrnU1cM0 fNXXSXqd/1ZXPUFmBQ28HjUaEFSzAPRUVqOtFrAY= Date: Fri, 14 May 2021 13:22:30 +0200 From: Greg KH To: Sergio Paracuellos Cc: Vinod Koul , Kishon Vijay Abraham I , "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" , linux-phy@lists.infradead.org, Rob Herring , linux-staging@lists.linux.dev, NeilBrown , Ilya Lipnitskiy Subject: Re: [PATCH RESEND v2 0/6] phy: ralink: mt7621-pci-phy: some improvements Message-ID: References: <20210508070930.5290-1-sergio.paracuellos@gmail.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210514_042234_213790_45EDF983 X-CRM114-Status: GOOD ( 18.61 ) X-BeenThere: linux-phy@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Linux Phy Mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-phy" Errors-To: linux-phy-bounces+linux-phy=archiver.kernel.org@lists.infradead.org On Fri, May 14, 2021 at 01:19:18PM +0200, Sergio Paracuellos wrote: > On Fri, May 14, 2021 at 12:46 PM Vinod Koul wrote: > > > > On 08-05-21, 09:09, Sergio Paracuellos wrote: > > > Hi all, > > > > > > This series contains some improvements in the pci phy driver > > > for MT7621 SoCs. > > > > > > MT7621 SoC clock driver has already mainlined in > > > 'commit 48df7a26f470 ("clk: ralink: add clock driver for mt7621 SoC")' > > > > > > Because of this we can update schema documentation and device tree > > > to add related clock entries and avoid custom architecture code > > > in favour of using the clock kernel framework to retrieve clock > > > frequency needed to properly configure the PCIe related Phys. > > > > > > After this changes there is no problem to properly enable this > > > driver for COMPILE_TEST. > > > > > > Configuration has also modified from 'tristate' to 'bool' depending > > > on PCI_MT7621 which seems to have more sense. > > > > Applied 2-6, thanks > > Thanks, Vinod. > > Greg, can you take patch 1 through your tree? Sure, can you resend it? thanks, greg k-h -- linux-phy mailing list linux-phy@lists.infradead.org https://lists.infradead.org/mailman/listinfo/linux-phy From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A9FA970 for ; Fri, 14 May 2021 11:22:33 +0000 (UTC) Received: by mail.kernel.org (Postfix) with ESMTPSA id 8B792613DE; Fri, 14 May 2021 11:22:32 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=linuxfoundation.org; s=korg; t=1620991353; bh=fdI4/WvFxLdOxw3z0CJfS4djdEHMKXDEj+klVKAPPdM=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=SfyuVtLk6E8Z65FAVs45sn4bhQlv74lXiwqfQ10FIfAcIv1uWX2qGOKNlzuX37A0V y8y/OzI4Z9TSvvbflhG9P0FK016w73qiejkBEIFf48S3YnGTV4owY+RRD7xrnU1cM0 fNXXSXqd/1ZXPUFmBQ28HjUaEFSzAPRUVqOtFrAY= Date: Fri, 14 May 2021 13:22:30 +0200 From: Greg KH To: Sergio Paracuellos Cc: Vinod Koul , Kishon Vijay Abraham I , "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" , linux-phy@lists.infradead.org, Rob Herring , linux-staging@lists.linux.dev, NeilBrown , Ilya Lipnitskiy Subject: Re: [PATCH RESEND v2 0/6] phy: ralink: mt7621-pci-phy: some improvements Message-ID: References: <20210508070930.5290-1-sergio.paracuellos@gmail.com> X-Mailing-List: linux-staging@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: On Fri, May 14, 2021 at 01:19:18PM +0200, Sergio Paracuellos wrote: > On Fri, May 14, 2021 at 12:46 PM Vinod Koul wrote: > > > > On 08-05-21, 09:09, Sergio Paracuellos wrote: > > > Hi all, > > > > > > This series contains some improvements in the pci phy driver > > > for MT7621 SoCs. > > > > > > MT7621 SoC clock driver has already mainlined in > > > 'commit 48df7a26f470 ("clk: ralink: add clock driver for mt7621 SoC")' > > > > > > Because of this we can update schema documentation and device tree > > > to add related clock entries and avoid custom architecture code > > > in favour of using the clock kernel framework to retrieve clock > > > frequency needed to properly configure the PCIe related Phys. > > > > > > After this changes there is no problem to properly enable this > > > driver for COMPILE_TEST. > > > > > > Configuration has also modified from 'tristate' to 'bool' depending > > > on PCI_MT7621 which seems to have more sense. > > > > Applied 2-6, thanks > > Thanks, Vinod. > > Greg, can you take patch 1 through your tree? Sure, can you resend it? thanks, greg k-h