From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 12424C47082 for ; Wed, 26 May 2021 13:20:04 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id C92B9613C7 for ; Wed, 26 May 2021 13:20:03 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org C92B9613C7 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linux.intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 5ACB86E12E; Wed, 26 May 2021 13:20:03 +0000 (UTC) Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by gabe.freedesktop.org (Postfix) with ESMTPS id 0C9F86E12E for ; Wed, 26 May 2021 13:20:02 +0000 (UTC) IronPort-SDR: qWukgk4fCGn+0KeAKeXh+pFExHUvDuAluknyDfOZyFmgwIjFxW/YmyIzkLugTwOFPmnWDitG/8 IJTxu9woaOrA== X-IronPort-AV: E=McAfee;i="6200,9189,9996"; a="223646701" X-IronPort-AV: E=Sophos;i="5.82,331,1613462400"; d="scan'208";a="223646701" Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 May 2021 06:20:01 -0700 IronPort-SDR: +anPhA5uDuJGOaaJVXgOdUi9q253IuPSIWBK6PiGBMl8fb40D1A/5yRzh4zElY9V8Yjcr0F7dh rSvGUFIrtWQg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.82,331,1613462400"; d="scan'208";a="409255924" Received: from stinkbox.fi.intel.com (HELO stinkbox) ([10.237.72.171]) by fmsmga007.fm.intel.com with SMTP; 26 May 2021 06:19:58 -0700 Received: by stinkbox (sSMTP sendmail emulation); Wed, 26 May 2021 16:19:58 +0300 Date: Wed, 26 May 2021 16:19:58 +0300 From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= To: Jani Nikula Message-ID: References: <20210526082903.26395-1-jani.nikula@intel.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20210526082903.26395-1-jani.nikula@intel.com> X-Patchwork-Hint: comment Subject: Re: [Intel-gfx] [PATCH] drm/i915/adl_p: enable MSO on pipe B X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: intel-gfx@lists.freedesktop.org Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" On Wed, May 26, 2021 at 11:29:03AM +0300, Jani Nikula wrote: > On ADL-P, it's possible to enable the stream splitter on pipe B in > addition to pipe A. > = > Bspec: 50174 > Cc: Uma Shankar > Cc: Ville Syrj=E4l=E4 > Signed-off-by: Jani Nikula I have a feeling I reviewed this already. But maybe I'm just imagining it. Reviewed-by: Ville Syrj=E4l=E4 > --- > drivers/gpu/drm/i915/display/intel_ddi.c | 7 +++++-- > 1 file changed, 5 insertions(+), 2 deletions(-) > = > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i= 915/display/intel_ddi.c > index 3d8918674153..4d6f1a206f56 100644 > --- a/drivers/gpu/drm/i915/display/intel_ddi.c > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c > @@ -4729,9 +4729,12 @@ void intel_ddi_init(struct drm_i915_private *dev_p= riv, enum port port) > = > dig_port->hpd_pulse =3D intel_dp_hpd_pulse; > = > - /* Splitter enable for eDP MSO is supported for pipe A only. */ > - if (dig_port->dp.mso_link_count) > + /* Splitter enable for eDP MSO is limited to certain pipes. */ > + if (dig_port->dp.mso_link_count) { > encoder->pipe_mask =3D BIT(PIPE_A); > + if (IS_ALDERLAKE_P(dev_priv)) > + encoder->pipe_mask |=3D BIT(PIPE_B); > + } > } > = > /* In theory we don't need the encoder->type check, but leave it just in > -- = > 2.20.1 -- = Ville Syrj=E4l=E4 Intel _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx