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From: Bjorn Andersson <bjorn.andersson@linaro.org>
To: Stephen Boyd <swboyd@chromium.org>
Cc: khsieh@codeaurora.org, robdclark@gmail.com, sean@poorly.run,
	vkoul@kernel.org, agross@kernel.org, robh+dt@kernel.org,
	devicetree@vger.kernel.org, abhinavk@codeaurora.org,
	aravindh@codeaurora.org, freedreno@lists.freedesktop.org,
	linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH v2] arm64/dts/qcom/sc7180: Add Display Port dt node
Date: Tue, 8 Jun 2021 17:34:01 -0500	[thread overview]
Message-ID: <YL/wWdRs6e/eECiC@yoga> (raw)
In-Reply-To: <CAE-0n50WP25kRQkWMVdDZGsZWBXwfbVSTFKyBLF7f8Mp3x2Wfg@mail.gmail.com>

On Tue 08 Jun 17:29 CDT 2021, Stephen Boyd wrote:

> Quoting Bjorn Andersson (2021-06-08 15:26:23)
> > On Tue 08 Jun 17:15 CDT 2021, Stephen Boyd wrote:
> >
> > > Quoting Bjorn Andersson (2021-06-07 16:31:47)
> > > > On Mon 07 Jun 12:48 CDT 2021, khsieh@codeaurora.org wrote:
> > > >
> > > > > Sorry about the confusion. What I meant is that even though DP controller is
> > > > > in the MDSS_GDSC
> > > > > power domain, DP PHY/PLL sources out of CX. The DP link clocks have a direct
> > > > > impact
> > > > > on the CX voltage corners. Therefore, we need to mention the CX power domain
> > > > > here. And, since
> > > > > we can associate only one OPP table with one device, we picked the DP link
> > > > > clock over other
> > > > > clocks.
> > > >
> > > > Thank you, that's a much more useful answer.
> > > >
> > > > Naturally I would think it would make more sense for the PHY/PLL driver
> > > > to ensure that CX is appropriately voted for then, but I think that
> > > > would result in it being the clock driver performing such vote and I'm
> > > > unsure how the opp table for that would look.
> > > >
> > > > @Stephen, what do you say?
> > > >
> > >
> > > Wouldn't the PHY be the one that sets some vote? So it wouldn't be the
> > > clk driver, and probably not from the clk ops, but instead come from the
> > > phy ops via phy_enable() and phy_configure().
> > >
> >
> > If I understand the logic correctly *_configure_dp_phy() will both
> > configure the vco clock and "request" the clock framework to change the
> > rate.
> >
> > So I presume what you're suggesting is that that would be the place to
> > cast the CX corner vote?
> 
> Yes that would be a place to make the CX vote. The problem is then I
> don't know where to drop the vote. Is that when the phy is disabled?

We do pass qcom_qmp_phy_power_off() and power down the DP part as DP
output is being disabled. So that sounds like a reasonable place to drop
the vote for the lowest performance state.

Regards,
Bjorn

  reply	other threads:[~2021-06-08 22:34 UTC|newest]

Thread overview: 21+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-06-03 16:09 [PATCH v2] arm64/dts/qcom/sc7180: Add Display Port dt node Kuogee Hsieh
2021-06-03 16:53 ` Bjorn Andersson
2021-06-03 21:28   ` khsieh
2021-06-03 21:35     ` Stephen Boyd
2021-06-03 21:56   ` khsieh
2021-06-06  5:07     ` Bjorn Andersson
2021-06-07 17:48       ` khsieh
2021-06-07 23:31         ` Bjorn Andersson
2021-06-08 22:15           ` Stephen Boyd
2021-06-08 22:26             ` Bjorn Andersson
2021-06-08 22:29               ` Stephen Boyd
2021-06-08 22:34                 ` Bjorn Andersson [this message]
2021-06-08 22:44                   ` Stephen Boyd
2021-06-08 23:10                     ` Bjorn Andersson
2021-06-10 16:54                       ` khsieh
2021-06-18 20:49                         ` Stephen Boyd
2021-06-18 21:41                           ` Bjorn Andersson
2021-06-22 20:23                             ` Stephen Boyd
2021-06-23  2:52                               ` Bjorn Andersson
2021-06-25 15:55                                 ` khsieh
2021-06-25 16:04                                   ` Bjorn Andersson

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