Re: [PATCH v6 00/14] Base for adding PowerPC 64-bit instructions

[David Gibson <david@gibson.dropbear.id.au>]

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On Tue, Jun 01, 2021 at 04:35:14PM -0300, matheus.ferst@eldorado.org.br wrote:
> From: Matheus Ferst <matheus.ferst@eldorado.org.br>
> 
> This series provides the basic infrastructure for adding the new 32/64-bit
> instructions in Power ISA 3.1 to target/ppc.

Applied to ppc-for-6.1.
> 
> v6:
> - Rebase on ppc-for-6.1;
> - Fix rebase error in patch 02/14;
> - Fix style errors;
> - REQUIRE_64BIT when L=1 in cmp/cmpi/cmpl/cmpli.
> 
> v5:
> - Rebase on ppc-for-6.1;
> - Change copyright line from new files;
> - Remove argument set from PNOP;
> - Add comments to explain helper_cfuged implementation;
> - New REQUIRE_ALTIVEC macro;
> - REQUIRE_ALTIVEC and REQUIRE_INSNS_FLAGS2 in trans_CFUGED;
> - cmp/cmpi/cmpl/cmpli moved to decodetree.
> 
> v4:
> - Rebase on ppc-for-6.1;
> - Fold do_ldst_D and do_ldst_X;
> - Add tcg_const_tl, used to share do_ldst_D and do_ldst_X code;
> - Unfold prefixed and non-prefixed loads/stores/addi to let non-prefixed insns use the non-prefixed formats;
> - PNOP invalid suffixes;
> - setbc/setbcr/stnbc/setnbcr implemented;
> - cfuged/vcfuged implemented;
> - addpcis moved to decodetree.
> 
> v3:
> - More changes for decodetree.
> - Cleanup exception/is_jmp logic to the point exception is removed.
> - Fold in Luis' isa check for prefixed insn support.
> - Share trans_* between prefixed and non-prefixed instructions.
> - Use macros to minimize the trans_* boilerplate.
> - Fix decode mistake for STHX/STHXU.
> 
> v2:
> - Store current pc in ctx instead of insn_size
> - Use separate decode files for 32- and 64-bit instructions
> - Improvements to the exception/is_jmp logic
> - Use translator_loop_temp_check()
> - Moved logic to prevent translation from crossing page boundaries
> - Additional instructions using decodetree: addis, pnop, loads/stores
> - Added check for prefixed insn support in cpu flags
> 
> 
> Matheus Ferst (5):
>   target/ppc: Implement setbc/setbcr/stnbc/setnbcr instructions
>   target/ppc: Implement cfuged instruction
>   target/ppc: Implement vcfuged instruction
>   target/ppc: Move addpcis to decodetree
>   target/ppc: Move cmp/cmpi/cmpl/cmpli to decodetree
> 
> Richard Henderson (9):
>   target/ppc: Introduce macros to check isa extensions
>   target/ppc: Move page crossing check to ppc_tr_translate_insn
>   target/ppc: Add infrastructure for prefixed insns
>   target/ppc: Move ADDI, ADDIS to decodetree, implement PADDI
>   target/ppc: Implement PNOP
>   target/ppc: Move D/DS/X-form integer loads to decodetree
>   target/ppc: Implement prefixed integer load instructions
>   target/ppc: Move D/DS/X-form integer stores to decodetree
>   target/ppc: Implement prefixed integer store instructions
> 
>  target/ppc/cpu.h                           |   1 +
>  target/ppc/helper.h                        |   1 +
>  target/ppc/insn32.decode                   | 126 +++++++
>  target/ppc/insn64.decode                   | 124 +++++++
>  target/ppc/int_helper.c                    |  62 ++++
>  target/ppc/meson.build                     |   9 +
>  target/ppc/translate.c                     | 391 +++++----------------
>  target/ppc/translate/fixedpoint-impl.c.inc | 279 +++++++++++++++
>  target/ppc/translate/vector-impl.c.inc     |  56 +++
>  9 files changed, 747 insertions(+), 302 deletions(-)
>  create mode 100644 target/ppc/insn32.decode
>  create mode 100644 target/ppc/insn64.decode
>  create mode 100644 target/ppc/translate/fixedpoint-impl.c.inc
>  create mode 100644 target/ppc/translate/vector-impl.c.inc
> 

-- 
David Gibson			| I'll have my music baroque, and my code
david AT gibson.dropbear.id.au	| minimalist, thank you.  NOT _the_ _other_
				| _way_ _around_!
http://www.ozlabs.org/~dgibson

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