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[35.195.168.105]) by smtp.gmail.com with ESMTPSA id p20sm2282579wmq.10.2021.06.02.03.58.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 02 Jun 2021 03:58:30 -0700 (PDT) Date: Wed, 2 Jun 2021 10:58:28 +0000 From: Quentin Perret To: Yanan Wang Subject: Re: [PATCH v5 5/6] KVM: arm64: Move I-cache flush to the fault handlers Message-ID: References: <20210415115032.35760-1-wangyanan55@huawei.com> <20210415115032.35760-6-wangyanan55@huawei.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20210415115032.35760-6-wangyanan55@huawei.com> Cc: kvm@vger.kernel.org, Marc Zyngier , linux-kernel@vger.kernel.org, Catalin Marinas , Will Deacon , kvmarm@lists.cs.columbia.edu, linux-arm-kernel@lists.infradead.org X-BeenThere: kvmarm@lists.cs.columbia.edu X-Mailman-Version: 2.1.14 Precedence: list List-Id: Where KVM/ARM decisions are made List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Errors-To: kvmarm-bounces@lists.cs.columbia.edu Sender: kvmarm-bounces@lists.cs.columbia.edu On Thursday 15 Apr 2021 at 19:50:31 (+0800), Yanan Wang wrote: > In this patch, we move invalidation of I-cache to the fault handlers to Nit: please avoid using 'This patch' in commit messages, see Documentation/process/submitting-patches.rst. > avoid unnecessary I-cache maintenances. On the map path, invalidate the > I-cache if we are going to create an executable stage-2 mapping for guest. > And on the permission path, invalidate the I-cache if we are going to add > an executable permission to the existing guest stage-2 mapping. > > Signed-off-by: Yanan Wang > --- > arch/arm64/include/asm/kvm_mmu.h | 15 -------------- > arch/arm64/kvm/hyp/pgtable.c | 35 +++++++++++++++++++++++++++++++- > arch/arm64/kvm/mmu.c | 9 +------- > 3 files changed, 35 insertions(+), 24 deletions(-) > > diff --git a/arch/arm64/include/asm/kvm_mmu.h b/arch/arm64/include/asm/kvm_mmu.h > index e9b163c5f023..155492fe5b15 100644 > --- a/arch/arm64/include/asm/kvm_mmu.h > +++ b/arch/arm64/include/asm/kvm_mmu.h > @@ -187,21 +187,6 @@ static inline bool vcpu_has_cache_enabled(struct kvm_vcpu *vcpu) > return (vcpu_read_sys_reg(vcpu, SCTLR_EL1) & 0b101) == 0b101; > } > > -static inline void __invalidate_icache_guest_page(kvm_pfn_t pfn, > - unsigned long size) > -{ > - if (icache_is_aliasing()) { > - /* any kind of VIPT cache */ > - __flush_icache_all(); > - } else if (is_kernel_in_hyp_mode() || !icache_is_vpipt()) { > - /* PIPT or VPIPT at EL2 (see comment in __kvm_tlb_flush_vmid_ipa) */ > - void *va = page_address(pfn_to_page(pfn)); > - > - invalidate_icache_range((unsigned long)va, > - (unsigned long)va + size); > - } > -} > - > void kvm_set_way_flush(struct kvm_vcpu *vcpu); > void kvm_toggle_cache(struct kvm_vcpu *vcpu, bool was_enabled); > > diff --git a/arch/arm64/kvm/hyp/pgtable.c b/arch/arm64/kvm/hyp/pgtable.c > index b480f6d1171e..9f4429d80df0 100644 > --- a/arch/arm64/kvm/hyp/pgtable.c > +++ b/arch/arm64/kvm/hyp/pgtable.c > @@ -568,6 +568,26 @@ static bool stage2_pte_cacheable(struct kvm_pgtable *pgt, kvm_pte_t pte) > return memattr == KVM_S2_MEMATTR(pgt, NORMAL); > } > > +static bool stage2_pte_executable(kvm_pte_t pte) > +{ > + return !(pte & KVM_PTE_LEAF_ATTR_HI_S2_XN); > +} > + > +static void stage2_invalidate_icache(void *addr, u64 size) > +{ > + if (icache_is_aliasing()) { > + /* Any kind of VIPT cache */ > + __flush_icache_all(); > + } else if (is_kernel_in_hyp_mode() || !icache_is_vpipt()) { > + /* > + * See comment in __kvm_tlb_flush_vmid_ipa(). > + * Invalidate PIPT, or VPIPT at EL2. > + */ > + invalidate_icache_range((unsigned long)addr, > + (unsigned long)addr + size); > + } > +} > + > static void stage2_put_pte(kvm_pte_t *ptep, struct kvm_s2_mmu *mmu, u64 addr, > u32 level, struct kvm_pgtable_mm_ops *mm_ops) > { > @@ -618,6 +638,10 @@ static int stage2_map_walker_try_leaf(u64 addr, u64 end, u32 level, > if (stage2_pte_cacheable(pgt, new) && !stage2_has_fwb(pgt)) > __flush_dcache_area(mm_ops->phys_to_virt(phys), > granule); > + > + if (stage2_pte_executable(new)) > + stage2_invalidate_icache(mm_ops->phys_to_virt(phys), > + granule); > } > > smp_store_release(ptep, new); > @@ -896,8 +920,17 @@ static int stage2_attr_walker(u64 addr, u64 end, u32 level, kvm_pte_t *ptep, > * but worst-case the access flag update gets lost and will be > * set on the next access instead. > */ > - if (data->pte != pte) > + if (data->pte != pte) { > + /* > + * Invalidate the instruction cache before updating > + * if we are going to add the executable permission > + * for the guest stage-2 PTE. > + */ > + if (!stage2_pte_executable(*ptep) && stage2_pte_executable(pte)) > + stage2_invalidate_icache(kvm_pte_follow(pte, data->mm_ops), > + kvm_granule_size(level)); > WRITE_ONCE(*ptep, pte); > + } As for the dcache stuff, it seems like this would be best placed in an optional mm_ops callback, and have the kernel implement it. Thanks, Quentin _______________________________________________ kvmarm mailing list kvmarm@lists.cs.columbia.edu https://lists.cs.columbia.edu/mailman/listinfo/kvmarm From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-14.1 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_ADSP_CUSTOM_MED,DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 60B42C47083 for ; Wed, 2 Jun 2021 11:09:57 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 268DB611CC for ; Wed, 2 Jun 2021 11:09:57 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 268DB611CC Authentication-Results: mail.kernel.org; dmarc=fail (p=reject dis=none) header.from=google.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:Cc:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=YE/fNI4JHVXcmWDWfcL1NkOTFqAAtbXDCpkg8ohdfVo=; b=pbNBHJe/2E3Rdy hzptHZIBjXCQT0d0N6mLGH+UB8IWERZvoPyLav8MKus7J2JM//dUPqrm11Ec/2tTYO2bwJBPSLvGb I1ZR8oDjmbUhZCvkXg0+ojdZEfsAewaalnTT2eBjujkx2r9EPqwjHnM27Q1UQCJQe9C73nbJJmKBo i0uhdnAtJD7Ly2Pdn9MgQr73nyPJXmry2CZIuw/kA4p9YoOwnZFuepphD1AB+myNerZqpvwMZ+TOG vY8NjjMLMyGkaUHc205WCHV64mcqGrASw4XehbeBbRuAd87KLgsprUME2EXjnpz3WtUtXBpnX2hkq fds71rb94tDvj+hEd4ig==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1loOjP-003adB-5Y; Wed, 02 Jun 2021 11:08:15 +0000 Received: from mail-wr1-x429.google.com ([2a00:1450:4864:20::429]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1loOa1-003W0O-GV for linux-arm-kernel@lists.infradead.org; Wed, 02 Jun 2021 10:58:35 +0000 Received: by mail-wr1-x429.google.com with SMTP id j14so1842490wrq.5 for ; Wed, 02 Jun 2021 03:58:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20161025; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to; bh=O4j3rnMAVVtQuafSexYtSyjSly5WDUnGVtpX8LTwkWk=; b=d9OMAA5JQL8jC8IxP/OtQ63ClDX5Ld+AUFGF/BIOaD/SPONLkodo+0jo+RoR5mTEoG PgEtpTeFjZuBJL9c8NqbqT4O2UEaEcx8ML3eRmuh0UsgOU9zhHUnaTUwSksBRv50EFc4 /5c1l39b3D/IhKxRwmtDrUarmu7vHmsK2uTIYSofXXK4E/7OAeHrYCBLWmlw0NiySvuD 8OQG/6n06I2QQCQrFJvnYGrFmG3Xm6Oa5OvJSwdktqi9f0XB5AWk5Z8d943IYaK4XrOZ NIJ+adU/E5fxPEDKhHTWUPvO89BHwHgJ1hxssujS/JX1wQNwa0PwvOnQC6krwwxh+nWU q3WQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to; bh=O4j3rnMAVVtQuafSexYtSyjSly5WDUnGVtpX8LTwkWk=; b=W3KabGSR+FdVGaAQ8uyZWOBsxUP7+36pvgq2bax1FH8iRLxCgENJ4nAA3spS97TK4N xchQs9WNNnoYmUzihk+xkfrn4xLv76tzz82va/DyKGeeYdCBzFOH2UVurnoa+/nbOobB 5UVXhsGSxzw6ga6KIiU2mbxy3BkHzcz/Lc/+pBQSa75NL4/6+2A4f3KfwhWck3vhpL8P LPrJo/vu8MYyzoDHqeRR9XaKLaBddkkeZq/Q9zjTS1utQYTbIp9JMiEkbDF8u5dvoofz hvY0i4NrTaZtLPm1VvwzJKFUiM04QlVikN2XcG1RODlK330jNAcprRvYUYKUxoA3mCAC J/7Q== X-Gm-Message-State: AOAM5334fKLAaZ1Dj5+oCHL9rjPMsmwi0PQ37pPJEfn5hDXL+/xhDCDh m+gi/5/DFqwl2AuIfvQJkXgdyw== X-Google-Smtp-Source: ABdhPJxQ4Mw6GmqjL/VfVeU2WxB50DVhQpumz9XVUbL+idgnhTuIw21b4d+fUny6pxwYk9C9Mijxyw== X-Received: by 2002:adf:f346:: with SMTP id e6mr5572912wrp.179.1622631511395; Wed, 02 Jun 2021 03:58:31 -0700 (PDT) Received: from google.com (105.168.195.35.bc.googleusercontent.com. [35.195.168.105]) by smtp.gmail.com with ESMTPSA id p20sm2282579wmq.10.2021.06.02.03.58.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 02 Jun 2021 03:58:30 -0700 (PDT) Date: Wed, 2 Jun 2021 10:58:28 +0000 From: Quentin Perret To: Yanan Wang Cc: Marc Zyngier , Will Deacon , Alexandru Elisei , kvmarm@lists.cs.columbia.edu, linux-arm-kernel@lists.infradead.org, kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Catalin Marinas , James Morse , Julien Thierry , Suzuki K Poulose , Gavin Shan , wanghaibin.wang@huawei.com, zhukeqian1@huawei.com, yuzenghui@huawei.com Subject: Re: [PATCH v5 5/6] KVM: arm64: Move I-cache flush to the fault handlers Message-ID: References: <20210415115032.35760-1-wangyanan55@huawei.com> <20210415115032.35760-6-wangyanan55@huawei.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20210415115032.35760-6-wangyanan55@huawei.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210602_035833_598318_F281C340 X-CRM114-Status: GOOD ( 27.21 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Thursday 15 Apr 2021 at 19:50:31 (+0800), Yanan Wang wrote: > In this patch, we move invalidation of I-cache to the fault handlers to Nit: please avoid using 'This patch' in commit messages, see Documentation/process/submitting-patches.rst. > avoid unnecessary I-cache maintenances. On the map path, invalidate the > I-cache if we are going to create an executable stage-2 mapping for guest. > And on the permission path, invalidate the I-cache if we are going to add > an executable permission to the existing guest stage-2 mapping. > > Signed-off-by: Yanan Wang > --- > arch/arm64/include/asm/kvm_mmu.h | 15 -------------- > arch/arm64/kvm/hyp/pgtable.c | 35 +++++++++++++++++++++++++++++++- > arch/arm64/kvm/mmu.c | 9 +------- > 3 files changed, 35 insertions(+), 24 deletions(-) > > diff --git a/arch/arm64/include/asm/kvm_mmu.h b/arch/arm64/include/asm/kvm_mmu.h > index e9b163c5f023..155492fe5b15 100644 > --- a/arch/arm64/include/asm/kvm_mmu.h > +++ b/arch/arm64/include/asm/kvm_mmu.h > @@ -187,21 +187,6 @@ static inline bool vcpu_has_cache_enabled(struct kvm_vcpu *vcpu) > return (vcpu_read_sys_reg(vcpu, SCTLR_EL1) & 0b101) == 0b101; > } > > -static inline void __invalidate_icache_guest_page(kvm_pfn_t pfn, > - unsigned long size) > -{ > - if (icache_is_aliasing()) { > - /* any kind of VIPT cache */ > - __flush_icache_all(); > - } else if (is_kernel_in_hyp_mode() || !icache_is_vpipt()) { > - /* PIPT or VPIPT at EL2 (see comment in __kvm_tlb_flush_vmid_ipa) */ > - void *va = page_address(pfn_to_page(pfn)); > - > - invalidate_icache_range((unsigned long)va, > - (unsigned long)va + size); > - } > -} > - > void kvm_set_way_flush(struct kvm_vcpu *vcpu); > void kvm_toggle_cache(struct kvm_vcpu *vcpu, bool was_enabled); > > diff --git a/arch/arm64/kvm/hyp/pgtable.c b/arch/arm64/kvm/hyp/pgtable.c > index b480f6d1171e..9f4429d80df0 100644 > --- a/arch/arm64/kvm/hyp/pgtable.c > +++ b/arch/arm64/kvm/hyp/pgtable.c > @@ -568,6 +568,26 @@ static bool stage2_pte_cacheable(struct kvm_pgtable *pgt, kvm_pte_t pte) > return memattr == KVM_S2_MEMATTR(pgt, NORMAL); > } > > +static bool stage2_pte_executable(kvm_pte_t pte) > +{ > + return !(pte & KVM_PTE_LEAF_ATTR_HI_S2_XN); > +} > + > +static void stage2_invalidate_icache(void *addr, u64 size) > +{ > + if (icache_is_aliasing()) { > + /* Any kind of VIPT cache */ > + __flush_icache_all(); > + } else if (is_kernel_in_hyp_mode() || !icache_is_vpipt()) { > + /* > + * See comment in __kvm_tlb_flush_vmid_ipa(). > + * Invalidate PIPT, or VPIPT at EL2. > + */ > + invalidate_icache_range((unsigned long)addr, > + (unsigned long)addr + size); > + } > +} > + > static void stage2_put_pte(kvm_pte_t *ptep, struct kvm_s2_mmu *mmu, u64 addr, > u32 level, struct kvm_pgtable_mm_ops *mm_ops) > { > @@ -618,6 +638,10 @@ static int stage2_map_walker_try_leaf(u64 addr, u64 end, u32 level, > if (stage2_pte_cacheable(pgt, new) && !stage2_has_fwb(pgt)) > __flush_dcache_area(mm_ops->phys_to_virt(phys), > granule); > + > + if (stage2_pte_executable(new)) > + stage2_invalidate_icache(mm_ops->phys_to_virt(phys), > + granule); > } > > smp_store_release(ptep, new); > @@ -896,8 +920,17 @@ static int stage2_attr_walker(u64 addr, u64 end, u32 level, kvm_pte_t *ptep, > * but worst-case the access flag update gets lost and will be > * set on the next access instead. > */ > - if (data->pte != pte) > + if (data->pte != pte) { > + /* > + * Invalidate the instruction cache before updating > + * if we are going to add the executable permission > + * for the guest stage-2 PTE. > + */ > + if (!stage2_pte_executable(*ptep) && stage2_pte_executable(pte)) > + stage2_invalidate_icache(kvm_pte_follow(pte, data->mm_ops), > + kvm_granule_size(level)); > WRITE_ONCE(*ptep, pte); > + } As for the dcache stuff, it seems like this would be best placed in an optional mm_ops callback, and have the kernel implement it. Thanks, Quentin _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-23.3 required=3.0 tests=BAYES_00,DKIMWL_WL_MED, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED,USER_IN_DEF_DKIM_WL autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9C83CC4708F for ; Wed, 2 Jun 2021 10:59:07 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 7C31B613AE for ; Wed, 2 Jun 2021 10:59:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231462AbhFBLAt (ORCPT ); Wed, 2 Jun 2021 07:00:49 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46498 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232093AbhFBLA1 (ORCPT ); Wed, 2 Jun 2021 07:00:27 -0400 Received: from mail-wr1-x42d.google.com (mail-wr1-x42d.google.com [IPv6:2a00:1450:4864:20::42d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DA601C061342 for ; Wed, 2 Jun 2021 03:58:32 -0700 (PDT) Received: by mail-wr1-x42d.google.com with SMTP id v23so1820588wrd.10 for ; Wed, 02 Jun 2021 03:58:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20161025; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to; bh=O4j3rnMAVVtQuafSexYtSyjSly5WDUnGVtpX8LTwkWk=; b=d9OMAA5JQL8jC8IxP/OtQ63ClDX5Ld+AUFGF/BIOaD/SPONLkodo+0jo+RoR5mTEoG PgEtpTeFjZuBJL9c8NqbqT4O2UEaEcx8ML3eRmuh0UsgOU9zhHUnaTUwSksBRv50EFc4 /5c1l39b3D/IhKxRwmtDrUarmu7vHmsK2uTIYSofXXK4E/7OAeHrYCBLWmlw0NiySvuD 8OQG/6n06I2QQCQrFJvnYGrFmG3Xm6Oa5OvJSwdktqi9f0XB5AWk5Z8d943IYaK4XrOZ NIJ+adU/E5fxPEDKhHTWUPvO89BHwHgJ1hxssujS/JX1wQNwa0PwvOnQC6krwwxh+nWU q3WQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to; bh=O4j3rnMAVVtQuafSexYtSyjSly5WDUnGVtpX8LTwkWk=; b=Gn6OqpqqStVCLispncODpo978Pcv+oUrTprOj9zr7AIu47pPrqSUOYYKZFGMib+GMU gEdWkBzX1KC84Vu3L2S0QCpQsPaOAxmKwoJ38xZRfM4szWE8H02FpM0Bffya16Yu7f27 V6WEAm/HOX5sE/QIFb+RiORU5gVytu+a97R3uWQ2nUmyIwzAvxVSziVmDqGIezh05c5N mYfaSUMd6MOmcQhlPu69nNXewwjWIdzx8rkjefe3Ntuo2hEMGeWKjjUGUez6x15bxe83 fIf/sRPKgJQvR98WQyq1wrwTWBwIyJ2cWz9jucdmgxnbzQYg36OmAkt8DRmuz8kYI1r6 lTjg== X-Gm-Message-State: AOAM530CP00PeBfAizmWdEw6WXjy1AciEFIlt3UFc1YAe5nWE+Op+wZD YtN+IZDpIwJdbxAzRLHisByctw== X-Google-Smtp-Source: ABdhPJxQ4Mw6GmqjL/VfVeU2WxB50DVhQpumz9XVUbL+idgnhTuIw21b4d+fUny6pxwYk9C9Mijxyw== X-Received: by 2002:adf:f346:: with SMTP id e6mr5572912wrp.179.1622631511395; Wed, 02 Jun 2021 03:58:31 -0700 (PDT) Received: from google.com (105.168.195.35.bc.googleusercontent.com. [35.195.168.105]) by smtp.gmail.com with ESMTPSA id p20sm2282579wmq.10.2021.06.02.03.58.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 02 Jun 2021 03:58:30 -0700 (PDT) Date: Wed, 2 Jun 2021 10:58:28 +0000 From: Quentin Perret To: Yanan Wang Cc: Marc Zyngier , Will Deacon , Alexandru Elisei , kvmarm@lists.cs.columbia.edu, linux-arm-kernel@lists.infradead.org, kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Catalin Marinas , James Morse , Julien Thierry , Suzuki K Poulose , Gavin Shan , wanghaibin.wang@huawei.com, zhukeqian1@huawei.com, yuzenghui@huawei.com Subject: Re: [PATCH v5 5/6] KVM: arm64: Move I-cache flush to the fault handlers Message-ID: References: <20210415115032.35760-1-wangyanan55@huawei.com> <20210415115032.35760-6-wangyanan55@huawei.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20210415115032.35760-6-wangyanan55@huawei.com> Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org On Thursday 15 Apr 2021 at 19:50:31 (+0800), Yanan Wang wrote: > In this patch, we move invalidation of I-cache to the fault handlers to Nit: please avoid using 'This patch' in commit messages, see Documentation/process/submitting-patches.rst. > avoid unnecessary I-cache maintenances. On the map path, invalidate the > I-cache if we are going to create an executable stage-2 mapping for guest. > And on the permission path, invalidate the I-cache if we are going to add > an executable permission to the existing guest stage-2 mapping. > > Signed-off-by: Yanan Wang > --- > arch/arm64/include/asm/kvm_mmu.h | 15 -------------- > arch/arm64/kvm/hyp/pgtable.c | 35 +++++++++++++++++++++++++++++++- > arch/arm64/kvm/mmu.c | 9 +------- > 3 files changed, 35 insertions(+), 24 deletions(-) > > diff --git a/arch/arm64/include/asm/kvm_mmu.h b/arch/arm64/include/asm/kvm_mmu.h > index e9b163c5f023..155492fe5b15 100644 > --- a/arch/arm64/include/asm/kvm_mmu.h > +++ b/arch/arm64/include/asm/kvm_mmu.h > @@ -187,21 +187,6 @@ static inline bool vcpu_has_cache_enabled(struct kvm_vcpu *vcpu) > return (vcpu_read_sys_reg(vcpu, SCTLR_EL1) & 0b101) == 0b101; > } > > -static inline void __invalidate_icache_guest_page(kvm_pfn_t pfn, > - unsigned long size) > -{ > - if (icache_is_aliasing()) { > - /* any kind of VIPT cache */ > - __flush_icache_all(); > - } else if (is_kernel_in_hyp_mode() || !icache_is_vpipt()) { > - /* PIPT or VPIPT at EL2 (see comment in __kvm_tlb_flush_vmid_ipa) */ > - void *va = page_address(pfn_to_page(pfn)); > - > - invalidate_icache_range((unsigned long)va, > - (unsigned long)va + size); > - } > -} > - > void kvm_set_way_flush(struct kvm_vcpu *vcpu); > void kvm_toggle_cache(struct kvm_vcpu *vcpu, bool was_enabled); > > diff --git a/arch/arm64/kvm/hyp/pgtable.c b/arch/arm64/kvm/hyp/pgtable.c > index b480f6d1171e..9f4429d80df0 100644 > --- a/arch/arm64/kvm/hyp/pgtable.c > +++ b/arch/arm64/kvm/hyp/pgtable.c > @@ -568,6 +568,26 @@ static bool stage2_pte_cacheable(struct kvm_pgtable *pgt, kvm_pte_t pte) > return memattr == KVM_S2_MEMATTR(pgt, NORMAL); > } > > +static bool stage2_pte_executable(kvm_pte_t pte) > +{ > + return !(pte & KVM_PTE_LEAF_ATTR_HI_S2_XN); > +} > + > +static void stage2_invalidate_icache(void *addr, u64 size) > +{ > + if (icache_is_aliasing()) { > + /* Any kind of VIPT cache */ > + __flush_icache_all(); > + } else if (is_kernel_in_hyp_mode() || !icache_is_vpipt()) { > + /* > + * See comment in __kvm_tlb_flush_vmid_ipa(). > + * Invalidate PIPT, or VPIPT at EL2. > + */ > + invalidate_icache_range((unsigned long)addr, > + (unsigned long)addr + size); > + } > +} > + > static void stage2_put_pte(kvm_pte_t *ptep, struct kvm_s2_mmu *mmu, u64 addr, > u32 level, struct kvm_pgtable_mm_ops *mm_ops) > { > @@ -618,6 +638,10 @@ static int stage2_map_walker_try_leaf(u64 addr, u64 end, u32 level, > if (stage2_pte_cacheable(pgt, new) && !stage2_has_fwb(pgt)) > __flush_dcache_area(mm_ops->phys_to_virt(phys), > granule); > + > + if (stage2_pte_executable(new)) > + stage2_invalidate_icache(mm_ops->phys_to_virt(phys), > + granule); > } > > smp_store_release(ptep, new); > @@ -896,8 +920,17 @@ static int stage2_attr_walker(u64 addr, u64 end, u32 level, kvm_pte_t *ptep, > * but worst-case the access flag update gets lost and will be > * set on the next access instead. > */ > - if (data->pte != pte) > + if (data->pte != pte) { > + /* > + * Invalidate the instruction cache before updating > + * if we are going to add the executable permission > + * for the guest stage-2 PTE. > + */ > + if (!stage2_pte_executable(*ptep) && stage2_pte_executable(pte)) > + stage2_invalidate_icache(kvm_pte_follow(pte, data->mm_ops), > + kvm_granule_size(level)); > WRITE_ONCE(*ptep, pte); > + } As for the dcache stuff, it seems like this would be best placed in an optional mm_ops callback, and have the kernel implement it. Thanks, Quentin