diff for duplicates of <YLelUPtti40D7DUl@kernel.org> diff --git a/a/1.txt b/N1/1.txt index bb73eef..3b90d93 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -28,7 +28,7 @@ Em Wed, Jun 02, 2021 at 11:45:42AM +0200, Borislav Petkov escreveu: > > > > --- > > 0-DAY CI Kernel Test Service, Intel Corporation -> > https://lists.01.org/hyperkitty/list/kbuild-all(a)lists.01.org +> > https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org > > 0day folks, please make a note if you can, to send such cpufeatures.h > header sync warnings to acme as he's verifying the feature bits modified @@ -51,7 +51,7 @@ fix, some comments added, etc. Some examples of what those scripts do: -⬢[acme(a)toolbox perf]$ tools/perf/trace/beauty/fadvise.sh +⬢[acme@toolbox perf]$ tools/perf/trace/beauty/fadvise.sh static const char *fadvise_advices[] = { [0] = "NORMAL", [1] = "RANDOM", @@ -60,7 +60,7 @@ static const char *fadvise_advices[] = { [4] = "DONTNEED", [5] = "NOREUSE", }; -⬢[acme(a)toolbox perf]$ tools/perf/trace/beauty/socket.sh +⬢[acme@toolbox perf]$ tools/perf/trace/beauty/socket.sh static const char *socket_families[] = { [0] = "UNSPEC", [1] = "LOCAL", @@ -108,17 +108,17 @@ static const char *socket_families[] = { [43] = "SMC", [44] = "XDP", }; -⬢[acme(a)toolbox perf]$ +⬢[acme@toolbox perf]$ Some of those files are used for building the tools, so that a tarball generated from: -⬢[acme(a)toolbox perf]$ make help | grep perf +⬢[acme@toolbox perf]$ make help | grep perf perf-tar-src-pkg - Build perf-5.13.0-rc4.tar source tarball perf-targz-src-pkg - Build perf-5.13.0-rc4.tar.gz source tarball perf-tarbz2-src-pkg - Build perf-5.13.0-rc4.tar.bz2 source tarball perf-tarxz-src-pkg - Build perf-5.13.0-rc4.tar.xz source tarball -⬢[acme(a)toolbox perf]$ +⬢[acme@toolbox perf]$ will build in older systems where things added to the updated copy of the kernel headers isn't present, so trying to update the file and then @@ -153,7 +153,7 @@ One more output that is x86 specific and allows this to work: 690.141 JS Watchdog/4259 msr:write_msr(msr: TSC_AUX, val: 3) 690.186 :0/0 msr:read_msr(msr: IA32_TSC_ADJUST) 759.016 :0/0 msr:read_msr(msr: IA32_TSC_ADJUST) - ^C[root(a)quaco ~]# + ^C[root@quaco ~]# Or look at the first 3 write_msr events for that IA32_TSC_DEADLINE to learn why it happens so often: @@ -190,7 +190,7 @@ One more output that is x86 specific and allows this to work: -⬢[acme(a)toolbox perf]$ tools/perf/trace/beauty/tracepoints/x86_msr.sh +⬢[acme@toolbox perf]$ tools/perf/trace/beauty/tracepoints/x86_msr.sh static const char *x86_MSRs[] = { [0x00000000] = "IA32_P5_MC_ADDR", [0x00000001] = "IA32_P5_MC_TYPE", @@ -497,4 +497,4 @@ static const char *x86_AMD_V_KVM_MSRs[] = { [0xc00102f0 - x86_AMD_V_KVM_MSRs_offset] = "AMD_PPIN_CTL", [0xc00102f1 - x86_AMD_V_KVM_MSRs_offset] = "AMD_PPIN", }; -⬢[acme(a)toolbox perf]$ +⬢[acme@toolbox perf]$ diff --git a/a/content_digest b/N1/content_digest index 9379372..54919ba 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -1,9 +1,16 @@ + "ref\020210602094153.GH1271937@shao2-debian\0" "ref\0YLdTRopUV9OyulSq@zn.tnic\0" "From\0Arnaldo Carvalho de Melo <acme@kernel.org>\0" - "Subject\0Re: [tip:x86/cpu 4/4] Warning: Kernel ABI header at 'tools/arch/x86/include/asm/cpufeatures.h' differs from latest version at 'arch/x86/include/asm/cpufeatures.h': 111< /* free ( 3*32+29) */\0" - "Date\0Wed, 02 Jun 2021 12:35:44 -0300\0" - "To\0kbuild-all@lists.01.org\0" - "\01:1\0" + "Subject\0Re: [tip:x86/cpu 4/4] Warning: Kernel ABI header at 'tools/arch/x86/include/asm/cpufeatures.h' differs from latest version at 'arch/x86/include/asm/cpufeatures.h': 111< /* free ( 3*32+29) */\0" + "Date\0Wed, 2 Jun 2021 12:35:44 -0300\0" + "To\0Borislav Petkov <bp@suse.de>\0" + "Cc\0kernel test robot <rong.a.chen@intel.com>" + Andrew Cooper <andrew.cooper3@citrix.com> + kbuild-all@lists.01.org + linux-kernel@vger.kernel.org + x86@kernel.org + " Peter Zijlstra <peterz@infradead.org>\0" + "\00:1\0" "b\0" "Em Wed, Jun 02, 2021 at 11:45:42AM +0200, Borislav Petkov escreveu:\n" "> + acme.\n" @@ -35,7 +42,7 @@ "> > \n" "> > ---\n" "> > 0-DAY CI Kernel Test Service, Intel Corporation\n" - "> > https://lists.01.org/hyperkitty/list/kbuild-all(a)lists.01.org\n" + "> > https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org\n" "> \n" "> 0day folks, please make a note if you can, to send such cpufeatures.h\n" "> header sync warnings to acme as he's verifying the feature bits modified\n" @@ -58,7 +65,7 @@ "\n" "\tSome examples of what those scripts do:\n" "\n" - "\342\254\242[acme(a)toolbox perf]$ tools/perf/trace/beauty/fadvise.sh\n" + "\342\254\242[acme@toolbox perf]$ tools/perf/trace/beauty/fadvise.sh\n" "static const char *fadvise_advices[] = {\n" "\t[0] = \"NORMAL\",\n" "\t[1] = \"RANDOM\",\n" @@ -67,7 +74,7 @@ "\t[4] = \"DONTNEED\",\n" "\t[5] = \"NOREUSE\",\n" "};\n" - "\342\254\242[acme(a)toolbox perf]$ tools/perf/trace/beauty/socket.sh\n" + "\342\254\242[acme@toolbox perf]$ tools/perf/trace/beauty/socket.sh\n" "static const char *socket_families[] = {\n" "\t[0] = \"UNSPEC\",\n" "\t[1] = \"LOCAL\",\n" @@ -115,17 +122,17 @@ "\t[43] = \"SMC\",\n" "\t[44] = \"XDP\",\n" "};\n" - "\342\254\242[acme(a)toolbox perf]$\n" + "\342\254\242[acme@toolbox perf]$\n" "\n" "\tSome of those files are used for building the tools, so that a\n" "tarball generated from:\n" "\n" - "\342\254\242[acme(a)toolbox perf]$ make help | grep perf\n" + "\342\254\242[acme@toolbox perf]$ make help | grep perf\n" " perf-tar-src-pkg - Build perf-5.13.0-rc4.tar source tarball\n" " perf-targz-src-pkg - Build perf-5.13.0-rc4.tar.gz source tarball\n" " perf-tarbz2-src-pkg - Build perf-5.13.0-rc4.tar.bz2 source tarball\n" " perf-tarxz-src-pkg - Build perf-5.13.0-rc4.tar.xz source tarball\n" - "\342\254\242[acme(a)toolbox perf]$\n" + "\342\254\242[acme@toolbox perf]$\n" "\n" "will build in older systems where things added to the updated copy of\n" "the kernel headers isn't present, so trying to update the file and then\n" @@ -160,7 +167,7 @@ " 690.141 JS Watchdog/4259 msr:write_msr(msr: TSC_AUX, val: 3)\n" " 690.186 :0/0 msr:read_msr(msr: IA32_TSC_ADJUST)\n" " 759.016 :0/0 msr:read_msr(msr: IA32_TSC_ADJUST)\n" - " ^C[root(a)quaco ~]#\n" + " ^C[root@quaco ~]#\n" " \n" " Or look at the first 3 write_msr events for that IA32_TSC_DEADLINE to learn why\n" " it happens so often:\n" @@ -197,7 +204,7 @@ "\n" "\n" "\n" - "\342\254\242[acme(a)toolbox perf]$ tools/perf/trace/beauty/tracepoints/x86_msr.sh \n" + "\342\254\242[acme@toolbox perf]$ tools/perf/trace/beauty/tracepoints/x86_msr.sh \n" "static const char *x86_MSRs[] = {\n" "\t[0x00000000] = \"IA32_P5_MC_ADDR\",\n" "\t[0x00000001] = \"IA32_P5_MC_TYPE\",\n" @@ -504,6 +511,6 @@ "\t[0xc00102f0 - x86_AMD_V_KVM_MSRs_offset] = \"AMD_PPIN_CTL\",\n" "\t[0xc00102f1 - x86_AMD_V_KVM_MSRs_offset] = \"AMD_PPIN\",\n" "};\n" - "\342\254\242[acme(a)toolbox perf]$" + "\342\254\242[acme@toolbox perf]$" -41164164ef713bdaaa0f0f2c21ff1d27988ec1f7dd6d8e259fb685cd91a26dec +9ffda5cd3546329bb74ff5aac7cb20f96d46de8fe077c0b9cbc74cd2381a1691
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