Re: [PATCH v2] target/ppc: fix single-step exception regression

[David Gibson <david@gibson.dropbear.id.au>]

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On Wed, Jun 02, 2021 at 09:51:03AM -0300, Luis Pires wrote:
> Commit 6086c75 (target/ppc: Replace POWERPC_EXCP_BRANCH with
> DISAS_NORETURN) broke the generation of exceptions when
> CPU_SINGLE_STEP or CPU_BRANCH_STEP were set, due to nip always being
> reset to the address of the current instruction.
> This fix leaves nip untouched when generating the exception.
> 
> Signed-off-by: Luis Pires <luis.pires@eldorado.org.br>
> Reported-by: Matheus Ferst <matheus.ferst@eldorado.org.br>

Applied to ppc-for-6.1, thanks.

> ---
> v2:
>  - Removed incorrect nip update from ppc_tr_tb_stop()
> 
>  target/ppc/translate.c | 5 ++---
>  1 file changed, 2 insertions(+), 3 deletions(-)
> 
> diff --git a/target/ppc/translate.c b/target/ppc/translate.c
> index ea200f9637..14a0bb7168 100644
> --- a/target/ppc/translate.c
> +++ b/target/ppc/translate.c
> @@ -4646,8 +4646,7 @@ static void gen_lookup_and_goto_ptr(DisasContext *ctx)
>          if (sse & GDBSTUB_SINGLE_STEP) {
>              gen_debug_exception(ctx);
>          } else if (sse & (CPU_SINGLE_STEP | CPU_BRANCH_STEP)) {
> -            uint32_t excp = gen_prep_dbgex(ctx);
> -            gen_exception(ctx, excp);
> +            gen_helper_raise_exception(cpu_env, tcg_constant_i32(gen_prep_dbgex(ctx)));
>          } else {
>              tcg_gen_exit_tb(NULL, 0);
>          }
> @@ -9128,7 +9127,7 @@ static void ppc_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs)
>          }
>          /* else CPU_SINGLE_STEP... */
>          if (nip <= 0x100 || nip > 0xf00) {
> -            gen_exception(ctx, gen_prep_dbgex(ctx));
> +            gen_helper_raise_exception(cpu_env, tcg_constant_i32(gen_prep_dbgex(ctx)));
>              return;
>          }
>      }

-- 
David Gibson			| I'll have my music baroque, and my code
david AT gibson.dropbear.id.au	| minimalist, thank you.  NOT _the_ _other_
				| _way_ _around_!
http://www.ozlabs.org/~dgibson

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