From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3616FC4743C for ; Mon, 14 Jun 2021 17:31:15 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 23641613BF for ; Mon, 14 Jun 2021 17:31:15 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233510AbhFNRdR (ORCPT ); Mon, 14 Jun 2021 13:33:17 -0400 Received: from mail-oi1-f182.google.com ([209.85.167.182]:36619 "EHLO mail-oi1-f182.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235509AbhFNRdQ (ORCPT ); Mon, 14 Jun 2021 13:33:16 -0400 Received: by mail-oi1-f182.google.com with SMTP id r16so14736492oiw.3 for ; Mon, 14 Jun 2021 10:31:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to; bh=xLux/4m5ofoODBdUbT7Ehl5QrekB6WictYiNsn1mOWI=; b=BmXLqT56g32BvBM3bzR5kCvabeozm5NrpVSpsIpgvkOTPWRPJlxZ/z/D73OSBK/6W5 6A5m0lZLGJQrk0wbOzn8azG01wcz2L7fv3KIn5f+5da/PfQrL2Jj+557OyLbNa9Lqrer 8KztQ1xFxpDOcaY4LfrVezdrtI0n1Y6Elzgs5dh8Hl1F/TueJNJO4giGIFov47dp7kTZ AGxDoJ2L3ig2rYKdAyR0GGF3tq0K5rTrQW3NZH8wS/6twS9QR0yZeHE5iOjmi1EOxiwm upaQMi/vLbzIB1+4Elozh2AyCxcKDl1DyEq3zToBpNm8On3qgzOIKhkII3HppjMv2rnf /qAA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to; bh=xLux/4m5ofoODBdUbT7Ehl5QrekB6WictYiNsn1mOWI=; b=jIlH1mvHOJHVOPEzXXz34wX3dHVDEaMd6U6xXCPJWXhY9o3eX5S55U/mtyYdQxjxlL O57Z8CZtmS7TVOwzhHLckpczbQNe+9RGCI82D6/94z1JesVrTzYE7pTgYhFC41w4UkUw VX1KAuQrNBb13SXvhKeAORK74E6z2Ay6WKHDXu+GWbCWpRu7ofa2NfbMtX3baDmrKh4a 9TKYDC1XM3uWTBYMYpY2DOxSiIFpGJSKwyPNvSRxJOoEb3niZ2xnjJcvM+MBRv6dvjYU mpHtdxO+w/EaTi4UZ7jJcIdxD5FOS6x3KuOG9tYV5KdP56ltrb4Sl7az2cYxmBxeuaTf ak+Q== X-Gm-Message-State: AOAM530NAVYXxOAObcAHmcyuqLrVXrdW+5GFYnT3H8Vln9acZnPK/uNK 56WKkM3rMJAmJlt7Mme7K2KmcQ== X-Google-Smtp-Source: ABdhPJw8j+3e3AKEgROrlKNjzXSDsCtRrFzgE31HIB9XuZeQfTHZGaNm//El0eGHEbYeJRKmO7lkjg== X-Received: by 2002:aca:ac47:: with SMTP id v68mr11196061oie.160.1623691813324; Mon, 14 Jun 2021 10:30:13 -0700 (PDT) Received: from yoga (104-57-184-186.lightspeed.austtx.sbcglobal.net. [104.57.184.186]) by smtp.gmail.com with ESMTPSA id f7sm3169502oot.36.2021.06.14.10.30.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 14 Jun 2021 10:30:12 -0700 (PDT) Date: Mon, 14 Jun 2021 12:30:10 -0500 From: Bjorn Andersson To: Rob Clark Cc: dri-devel@lists.freedesktop.org, iommu@lists.linux-foundation.org, freedreno@lists.freedesktop.org, linux-arm-msm@vger.kernel.org, Jordan Crouse , Jordan Crouse , Rob Clark , Will Deacon , Robin Murphy , Joerg Roedel , "Isaac J. Manjarres" , John Stultz , Krishna Reddy , Sai Prakash Ranjan , "moderated list:ARM SMMU DRIVERS" , open list Subject: Re: [PATCH v5 2/5] iommu/arm-smmu-qcom: Add an adreno-smmu-priv callback to get pagefault info Message-ID: References: <20210610214431.539029-1-robdclark@gmail.com> <20210610214431.539029-3-robdclark@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20210610214431.539029-3-robdclark@gmail.com> Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org On Thu 10 Jun 16:44 CDT 2021, Rob Clark wrote: > From: Jordan Crouse > > Add a callback in adreno-smmu-priv to read interesting SMMU > registers to provide an opportunity for a richer debug experience > in the GPU driver. > > Signed-off-by: Jordan Crouse > Signed-off-by: Rob Clark I presume this implies that more generic options has been discussed. Regardless, if further conclusions are made in that regard I expect that this could serve as a base for such efforts. Reviewed-by: Bjorn Andersson Regards, Bjorn > --- > drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 17 ++++++++++++ > drivers/iommu/arm/arm-smmu/arm-smmu.h | 2 ++ > include/linux/adreno-smmu-priv.h | 31 +++++++++++++++++++++- > 3 files changed, 49 insertions(+), 1 deletion(-) > > diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c > index 98b3a1c2a181..b2e31ea84128 100644 > --- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c > +++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c > @@ -32,6 +32,22 @@ static void qcom_adreno_smmu_write_sctlr(struct arm_smmu_device *smmu, int idx, > arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_SCTLR, reg); > } > > +static void qcom_adreno_smmu_get_fault_info(const void *cookie, > + struct adreno_smmu_fault_info *info) > +{ > + struct arm_smmu_domain *smmu_domain = (void *)cookie; > + struct arm_smmu_cfg *cfg = &smmu_domain->cfg; > + struct arm_smmu_device *smmu = smmu_domain->smmu; > + > + info->fsr = arm_smmu_cb_read(smmu, cfg->cbndx, ARM_SMMU_CB_FSR); > + info->fsynr0 = arm_smmu_cb_read(smmu, cfg->cbndx, ARM_SMMU_CB_FSYNR0); > + info->fsynr1 = arm_smmu_cb_read(smmu, cfg->cbndx, ARM_SMMU_CB_FSYNR1); > + info->far = arm_smmu_cb_readq(smmu, cfg->cbndx, ARM_SMMU_CB_FAR); > + info->cbfrsynra = arm_smmu_gr1_read(smmu, ARM_SMMU_GR1_CBFRSYNRA(cfg->cbndx)); > + info->ttbr0 = arm_smmu_cb_read(smmu, cfg->cbndx, ARM_SMMU_CB_TTBR0); > + info->contextidr = arm_smmu_cb_read(smmu, cfg->cbndx, ARM_SMMU_CB_CONTEXTIDR); > +} > + > #define QCOM_ADRENO_SMMU_GPU_SID 0 > > static bool qcom_adreno_smmu_is_gpu_device(struct device *dev) > @@ -156,6 +172,7 @@ static int qcom_adreno_smmu_init_context(struct arm_smmu_domain *smmu_domain, > priv->cookie = smmu_domain; > priv->get_ttbr1_cfg = qcom_adreno_smmu_get_ttbr1_cfg; > priv->set_ttbr0_cfg = qcom_adreno_smmu_set_ttbr0_cfg; > + priv->get_fault_info = qcom_adreno_smmu_get_fault_info; > > return 0; > } > diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu.h b/drivers/iommu/arm/arm-smmu/arm-smmu.h > index c31a59d35c64..84c21c4b0691 100644 > --- a/drivers/iommu/arm/arm-smmu/arm-smmu.h > +++ b/drivers/iommu/arm/arm-smmu/arm-smmu.h > @@ -224,6 +224,8 @@ enum arm_smmu_cbar_type { > #define ARM_SMMU_CB_FSYNR0 0x68 > #define ARM_SMMU_FSYNR0_WNR BIT(4) > > +#define ARM_SMMU_CB_FSYNR1 0x6c > + > #define ARM_SMMU_CB_S1_TLBIVA 0x600 > #define ARM_SMMU_CB_S1_TLBIASID 0x610 > #define ARM_SMMU_CB_S1_TLBIVAL 0x620 > diff --git a/include/linux/adreno-smmu-priv.h b/include/linux/adreno-smmu-priv.h > index a889f28afb42..53fe32fb9214 100644 > --- a/include/linux/adreno-smmu-priv.h > +++ b/include/linux/adreno-smmu-priv.h > @@ -8,6 +8,32 @@ > > #include > > +/** > + * struct adreno_smmu_fault_info - container for key fault information > + * > + * @far: The faulting IOVA from ARM_SMMU_CB_FAR > + * @ttbr0: The current TTBR0 pagetable from ARM_SMMU_CB_TTBR0 > + * @contextidr: The value of ARM_SMMU_CB_CONTEXTIDR > + * @fsr: The fault status from ARM_SMMU_CB_FSR > + * @fsynr0: The value of FSYNR0 from ARM_SMMU_CB_FSYNR0 > + * @fsynr1: The value of FSYNR1 from ARM_SMMU_CB_FSYNR0 > + * @cbfrsynra: The value of CBFRSYNRA from ARM_SMMU_GR1_CBFRSYNRA(idx) > + * > + * This struct passes back key page fault information to the GPU driver > + * through the get_fault_info function pointer. > + * The GPU driver can use this information to print informative > + * log messages and provide deeper GPU specific insight into the fault. > + */ > +struct adreno_smmu_fault_info { > + u64 far; > + u64 ttbr0; > + u32 contextidr; > + u32 fsr; > + u32 fsynr0; > + u32 fsynr1; > + u32 cbfrsynra; > +}; > + > /** > * struct adreno_smmu_priv - private interface between adreno-smmu and GPU > * > @@ -17,6 +43,8 @@ > * @set_ttbr0_cfg: Set the TTBR0 config for the GPUs context bank. A > * NULL config disables TTBR0 translation, otherwise > * TTBR0 translation is enabled with the specified cfg > + * @get_fault_info: Called by the GPU fault handler to get information about > + * the fault > * > * The GPU driver (drm/msm) and adreno-smmu work together for controlling > * the GPU's SMMU instance. This is by necessity, as the GPU is directly > @@ -31,6 +59,7 @@ struct adreno_smmu_priv { > const void *cookie; > const struct io_pgtable_cfg *(*get_ttbr1_cfg)(const void *cookie); > int (*set_ttbr0_cfg)(const void *cookie, const struct io_pgtable_cfg *cfg); > + void (*get_fault_info)(const void *cookie, struct adreno_smmu_fault_info *info); > }; > > -#endif /* __ADRENO_SMMU_PRIV_H */ > \ No newline at end of file > +#endif /* __ADRENO_SMMU_PRIV_H */ > -- > 2.31.1 > From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6EEEBC2B9F4 for ; Mon, 14 Jun 2021 17:30:19 +0000 (UTC) Received: from smtp2.osuosl.org (smtp2.osuosl.org [140.211.166.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 28ED261378 for ; Mon, 14 Jun 2021 17:30:18 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 28ED261378 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linaro.org Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=iommu-bounces@lists.linux-foundation.org Received: from localhost (localhost [127.0.0.1]) by smtp2.osuosl.org (Postfix) with ESMTP id E7F0440392; Mon, 14 Jun 2021 17:30:17 +0000 (UTC) X-Virus-Scanned: amavisd-new at osuosl.org Received: from smtp2.osuosl.org ([127.0.0.1]) by localhost (smtp2.osuosl.org [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id nSZ4InIB3Wis; Mon, 14 Jun 2021 17:30:16 +0000 (UTC) Received: from lists.linuxfoundation.org (lf-lists.osuosl.org [140.211.9.56]) by smtp2.osuosl.org (Postfix) with ESMTPS id A9CBA40270; Mon, 14 Jun 2021 17:30:16 +0000 (UTC) Received: from lf-lists.osuosl.org (localhost [127.0.0.1]) by lists.linuxfoundation.org (Postfix) with ESMTP id 793CFC000D; Mon, 14 Jun 2021 17:30:16 +0000 (UTC) Received: from smtp1.osuosl.org (smtp1.osuosl.org [IPv6:2605:bc80:3010::138]) by lists.linuxfoundation.org (Postfix) with ESMTP id 66AEDC000B for ; Mon, 14 Jun 2021 17:30:15 +0000 (UTC) Received: from localhost (localhost [127.0.0.1]) by smtp1.osuosl.org (Postfix) with ESMTP id 3A19983AAC for ; Mon, 14 Jun 2021 17:30:15 +0000 (UTC) X-Virus-Scanned: amavisd-new at osuosl.org Authentication-Results: smtp1.osuosl.org (amavisd-new); dkim=pass (2048-bit key) header.d=linaro.org Received: from smtp1.osuosl.org ([127.0.0.1]) by localhost (smtp1.osuosl.org [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id BSHo4_G8_S53 for ; Mon, 14 Jun 2021 17:30:14 +0000 (UTC) X-Greylist: whitelisted by SQLgrey-1.8.0 Received: from mail-oi1-x232.google.com (mail-oi1-x232.google.com [IPv6:2607:f8b0:4864:20::232]) by smtp1.osuosl.org (Postfix) with ESMTPS id 619518374F for ; Mon, 14 Jun 2021 17:30:14 +0000 (UTC) Received: by mail-oi1-x232.google.com with SMTP id t140so15155174oih.0 for ; Mon, 14 Jun 2021 10:30:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to; bh=xLux/4m5ofoODBdUbT7Ehl5QrekB6WictYiNsn1mOWI=; b=BmXLqT56g32BvBM3bzR5kCvabeozm5NrpVSpsIpgvkOTPWRPJlxZ/z/D73OSBK/6W5 6A5m0lZLGJQrk0wbOzn8azG01wcz2L7fv3KIn5f+5da/PfQrL2Jj+557OyLbNa9Lqrer 8KztQ1xFxpDOcaY4LfrVezdrtI0n1Y6Elzgs5dh8Hl1F/TueJNJO4giGIFov47dp7kTZ AGxDoJ2L3ig2rYKdAyR0GGF3tq0K5rTrQW3NZH8wS/6twS9QR0yZeHE5iOjmi1EOxiwm upaQMi/vLbzIB1+4Elozh2AyCxcKDl1DyEq3zToBpNm8On3qgzOIKhkII3HppjMv2rnf /qAA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to; bh=xLux/4m5ofoODBdUbT7Ehl5QrekB6WictYiNsn1mOWI=; b=Pwj08BAuQYLybtNeMVWe5rMsIkJJLmjZnxR5wesZXiXv23KLtW+kYej590T3XfelIB 8wdfkxJz4N6gZx9ce3V8xua+pMhEFm8d5ZKdunV/b8SXt801hhRQ9shvhEmBSkMBN1AA 9s2+eYjMFGX3hmRhDcojYp5QryeZb7B8X7FMWINxNdLvY+2oEDwUZDQ6wFjiTiFxpiGs W0rURZvtqdktVuyN70BerTTffd4Cih1Ow8HP2/VdewYyLrQ8+JSoOvrRGbFGmgzq41o1 TYAGm8ybxjIrNZ8M9n5yU1lCTxIFobhz+E6JWkil3Dizps3qOU/OCD7FuGxE39iWsbVH cnYg== X-Gm-Message-State: AOAM5335LANAGv1u9vDpob+BV3chEKN0kJKwU2CldoF2YEMIKMoJmu9j zo9GhWvmf9YqvUQ34JiZhKSKqA== X-Google-Smtp-Source: ABdhPJw8j+3e3AKEgROrlKNjzXSDsCtRrFzgE31HIB9XuZeQfTHZGaNm//El0eGHEbYeJRKmO7lkjg== X-Received: by 2002:aca:ac47:: with SMTP id v68mr11196061oie.160.1623691813324; Mon, 14 Jun 2021 10:30:13 -0700 (PDT) Received: from yoga (104-57-184-186.lightspeed.austtx.sbcglobal.net. [104.57.184.186]) by smtp.gmail.com with ESMTPSA id f7sm3169502oot.36.2021.06.14.10.30.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 14 Jun 2021 10:30:12 -0700 (PDT) Date: Mon, 14 Jun 2021 12:30:10 -0500 From: Bjorn Andersson To: Rob Clark Subject: Re: [PATCH v5 2/5] iommu/arm-smmu-qcom: Add an adreno-smmu-priv callback to get pagefault info Message-ID: References: <20210610214431.539029-1-robdclark@gmail.com> <20210610214431.539029-3-robdclark@gmail.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20210610214431.539029-3-robdclark@gmail.com> Cc: Rob Clark , "Isaac J. Manjarres" , open list , Will Deacon , linux-arm-msm@vger.kernel.org, Jordan Crouse , dri-devel@lists.freedesktop.org, iommu@lists.linux-foundation.org, John Stultz , freedreno@lists.freedesktop.org, "moderated list:ARM SMMU DRIVERS" , Robin Murphy X-BeenThere: iommu@lists.linux-foundation.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: Development issues for Linux IOMMU support List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Errors-To: iommu-bounces@lists.linux-foundation.org Sender: "iommu" On Thu 10 Jun 16:44 CDT 2021, Rob Clark wrote: > From: Jordan Crouse > > Add a callback in adreno-smmu-priv to read interesting SMMU > registers to provide an opportunity for a richer debug experience > in the GPU driver. > > Signed-off-by: Jordan Crouse > Signed-off-by: Rob Clark I presume this implies that more generic options has been discussed. Regardless, if further conclusions are made in that regard I expect that this could serve as a base for such efforts. Reviewed-by: Bjorn Andersson Regards, Bjorn > --- > drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 17 ++++++++++++ > drivers/iommu/arm/arm-smmu/arm-smmu.h | 2 ++ > include/linux/adreno-smmu-priv.h | 31 +++++++++++++++++++++- > 3 files changed, 49 insertions(+), 1 deletion(-) > > diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c > index 98b3a1c2a181..b2e31ea84128 100644 > --- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c > +++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c > @@ -32,6 +32,22 @@ static void qcom_adreno_smmu_write_sctlr(struct arm_smmu_device *smmu, int idx, > arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_SCTLR, reg); > } > > +static void qcom_adreno_smmu_get_fault_info(const void *cookie, > + struct adreno_smmu_fault_info *info) > +{ > + struct arm_smmu_domain *smmu_domain = (void *)cookie; > + struct arm_smmu_cfg *cfg = &smmu_domain->cfg; > + struct arm_smmu_device *smmu = smmu_domain->smmu; > + > + info->fsr = arm_smmu_cb_read(smmu, cfg->cbndx, ARM_SMMU_CB_FSR); > + info->fsynr0 = arm_smmu_cb_read(smmu, cfg->cbndx, ARM_SMMU_CB_FSYNR0); > + info->fsynr1 = arm_smmu_cb_read(smmu, cfg->cbndx, ARM_SMMU_CB_FSYNR1); > + info->far = arm_smmu_cb_readq(smmu, cfg->cbndx, ARM_SMMU_CB_FAR); > + info->cbfrsynra = arm_smmu_gr1_read(smmu, ARM_SMMU_GR1_CBFRSYNRA(cfg->cbndx)); > + info->ttbr0 = arm_smmu_cb_read(smmu, cfg->cbndx, ARM_SMMU_CB_TTBR0); > + info->contextidr = arm_smmu_cb_read(smmu, cfg->cbndx, ARM_SMMU_CB_CONTEXTIDR); > +} > + > #define QCOM_ADRENO_SMMU_GPU_SID 0 > > static bool qcom_adreno_smmu_is_gpu_device(struct device *dev) > @@ -156,6 +172,7 @@ static int qcom_adreno_smmu_init_context(struct arm_smmu_domain *smmu_domain, > priv->cookie = smmu_domain; > priv->get_ttbr1_cfg = qcom_adreno_smmu_get_ttbr1_cfg; > priv->set_ttbr0_cfg = qcom_adreno_smmu_set_ttbr0_cfg; > + priv->get_fault_info = qcom_adreno_smmu_get_fault_info; > > return 0; > } > diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu.h b/drivers/iommu/arm/arm-smmu/arm-smmu.h > index c31a59d35c64..84c21c4b0691 100644 > --- a/drivers/iommu/arm/arm-smmu/arm-smmu.h > +++ b/drivers/iommu/arm/arm-smmu/arm-smmu.h > @@ -224,6 +224,8 @@ enum arm_smmu_cbar_type { > #define ARM_SMMU_CB_FSYNR0 0x68 > #define ARM_SMMU_FSYNR0_WNR BIT(4) > > +#define ARM_SMMU_CB_FSYNR1 0x6c > + > #define ARM_SMMU_CB_S1_TLBIVA 0x600 > #define ARM_SMMU_CB_S1_TLBIASID 0x610 > #define ARM_SMMU_CB_S1_TLBIVAL 0x620 > diff --git a/include/linux/adreno-smmu-priv.h b/include/linux/adreno-smmu-priv.h > index a889f28afb42..53fe32fb9214 100644 > --- a/include/linux/adreno-smmu-priv.h > +++ b/include/linux/adreno-smmu-priv.h > @@ -8,6 +8,32 @@ > > #include > > +/** > + * struct adreno_smmu_fault_info - container for key fault information > + * > + * @far: The faulting IOVA from ARM_SMMU_CB_FAR > + * @ttbr0: The current TTBR0 pagetable from ARM_SMMU_CB_TTBR0 > + * @contextidr: The value of ARM_SMMU_CB_CONTEXTIDR > + * @fsr: The fault status from ARM_SMMU_CB_FSR > + * @fsynr0: The value of FSYNR0 from ARM_SMMU_CB_FSYNR0 > + * @fsynr1: The value of FSYNR1 from ARM_SMMU_CB_FSYNR0 > + * @cbfrsynra: The value of CBFRSYNRA from ARM_SMMU_GR1_CBFRSYNRA(idx) > + * > + * This struct passes back key page fault information to the GPU driver > + * through the get_fault_info function pointer. > + * The GPU driver can use this information to print informative > + * log messages and provide deeper GPU specific insight into the fault. > + */ > +struct adreno_smmu_fault_info { > + u64 far; > + u64 ttbr0; > + u32 contextidr; > + u32 fsr; > + u32 fsynr0; > + u32 fsynr1; > + u32 cbfrsynra; > +}; > + > /** > * struct adreno_smmu_priv - private interface between adreno-smmu and GPU > * > @@ -17,6 +43,8 @@ > * @set_ttbr0_cfg: Set the TTBR0 config for the GPUs context bank. A > * NULL config disables TTBR0 translation, otherwise > * TTBR0 translation is enabled with the specified cfg > + * @get_fault_info: Called by the GPU fault handler to get information about > + * the fault > * > * The GPU driver (drm/msm) and adreno-smmu work together for controlling > * the GPU's SMMU instance. This is by necessity, as the GPU is directly > @@ -31,6 +59,7 @@ struct adreno_smmu_priv { > const void *cookie; > const struct io_pgtable_cfg *(*get_ttbr1_cfg)(const void *cookie); > int (*set_ttbr0_cfg)(const void *cookie, const struct io_pgtable_cfg *cfg); > + void (*get_fault_info)(const void *cookie, struct adreno_smmu_fault_info *info); > }; > > -#endif /* __ADRENO_SMMU_PRIV_H */ > \ No newline at end of file > +#endif /* __ADRENO_SMMU_PRIV_H */ > -- > 2.31.1 > _______________________________________________ iommu mailing list iommu@lists.linux-foundation.org https://lists.linuxfoundation.org/mailman/listinfo/iommu From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.9 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 850C3C2B9F4 for ; Mon, 14 Jun 2021 17:32:48 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 3E0CB61350 for ; Mon, 14 Jun 2021 17:32:48 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 3E0CB61350 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linaro.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=GMKvf3AIqe2Raht1wiM3E2PnXNb5Iev0iOk3Un+4RlY=; b=pD3M61RQkpgYaE W5zXmtniTldDP44qprHwYLmskoIAnRfIVE86eXLJROpyifvhA+4d8dihwKFiP4tlZGWfNOt3Q1Vr6 E4gkj/rEtg23WoDRWNKwSQ9Eos9NQ8o8N1U58ZMMKtabsPgvdmmo9Lw2BRfWZvZwgH4AULLvZZQFw BUZOOKwQpqmGZum07Sq3mmC7+dCTOCLEAA8YVRB8Wu3OB2wfLWoTygws6ue6SYAgVfWnI3TzuHVmb MlcOWuM/47+u+lZmpBz/srr09CxgXFfafT+7pPjciSyu/yVDNkPD59JWMncx8fDg82UuZHvvXpzjn H5ThhXxiuYEe28vJ7/2Q==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1lsqQi-00FRFg-5m; Mon, 14 Jun 2021 17:31:20 +0000 Received: from mail-oi1-f180.google.com ([209.85.167.180]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1lsqQc-00FRED-VW for linux-arm-kernel@lists.infradead.org; Mon, 14 Jun 2021 17:31:16 +0000 Received: by mail-oi1-f180.google.com with SMTP id q10so10929857oij.5 for ; Mon, 14 Jun 2021 10:31:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to; bh=xLux/4m5ofoODBdUbT7Ehl5QrekB6WictYiNsn1mOWI=; b=BmXLqT56g32BvBM3bzR5kCvabeozm5NrpVSpsIpgvkOTPWRPJlxZ/z/D73OSBK/6W5 6A5m0lZLGJQrk0wbOzn8azG01wcz2L7fv3KIn5f+5da/PfQrL2Jj+557OyLbNa9Lqrer 8KztQ1xFxpDOcaY4LfrVezdrtI0n1Y6Elzgs5dh8Hl1F/TueJNJO4giGIFov47dp7kTZ AGxDoJ2L3ig2rYKdAyR0GGF3tq0K5rTrQW3NZH8wS/6twS9QR0yZeHE5iOjmi1EOxiwm upaQMi/vLbzIB1+4Elozh2AyCxcKDl1DyEq3zToBpNm8On3qgzOIKhkII3HppjMv2rnf /qAA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to; bh=xLux/4m5ofoODBdUbT7Ehl5QrekB6WictYiNsn1mOWI=; b=qjDjxlGe7EMBizCGmeAEuVG+AaoIGogDgymNvSOAqDMen6jX0udJPcZakH+FEzxGKZ 7ozc0iYzi7UfTDqxWeP/MnqriCQ780N8g5zfF3ibG1ow69QnoT+m/pgREZ3VE+bjhHkx QW1hzfOi+GVCnCITY9rqeRpH68S3EldfgiTq3Em/RT9/L7G9amfKihIZ9ICse/wdPx6T sZcL84Sg9wJZLh6O0izO0O1Tzy4cESDIXKM6BnsEgyFPxjkmD4Z78XNEcMflaLYFHy1y ExdYkcbWx5E5M17jvayJkLl3xVf4zmx1JS+D2LjREZhWeZcGDkLid0nRpagKpjqth0sB Ykog== X-Gm-Message-State: AOAM5327GdOhCKBl5A/E4MbaCxSpAT/VFzVWxZC7RmBqsE0Qfz/QcaPq jh7H8+n7YVg1ydwtrWfA9+AoTQ== X-Google-Smtp-Source: ABdhPJw8j+3e3AKEgROrlKNjzXSDsCtRrFzgE31HIB9XuZeQfTHZGaNm//El0eGHEbYeJRKmO7lkjg== X-Received: by 2002:aca:ac47:: with SMTP id v68mr11196061oie.160.1623691813324; Mon, 14 Jun 2021 10:30:13 -0700 (PDT) Received: from yoga (104-57-184-186.lightspeed.austtx.sbcglobal.net. [104.57.184.186]) by smtp.gmail.com with ESMTPSA id f7sm3169502oot.36.2021.06.14.10.30.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 14 Jun 2021 10:30:12 -0700 (PDT) Date: Mon, 14 Jun 2021 12:30:10 -0500 From: Bjorn Andersson To: Rob Clark Subject: Re: [PATCH v5 2/5] iommu/arm-smmu-qcom: Add an adreno-smmu-priv callback to get pagefault info Message-ID: References: <20210610214431.539029-1-robdclark@gmail.com> <20210610214431.539029-3-robdclark@gmail.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20210610214431.539029-3-robdclark@gmail.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210614_103115_037864_AEDF42B8 X-CRM114-Status: GOOD ( 28.63 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Rob Clark , "Isaac J. Manjarres" , Sai Prakash Ranjan , open list , Will Deacon , linux-arm-msm@vger.kernel.org, Joerg Roedel , Jordan Crouse , dri-devel@lists.freedesktop.org, Jordan Crouse , iommu@lists.linux-foundation.org, John Stultz , freedreno@lists.freedesktop.org, "moderated list:ARM SMMU DRIVERS" , Robin Murphy Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Thu 10 Jun 16:44 CDT 2021, Rob Clark wrote: > From: Jordan Crouse > > Add a callback in adreno-smmu-priv to read interesting SMMU > registers to provide an opportunity for a richer debug experience > in the GPU driver. > > Signed-off-by: Jordan Crouse > Signed-off-by: Rob Clark I presume this implies that more generic options has been discussed. Regardless, if further conclusions are made in that regard I expect that this could serve as a base for such efforts. Reviewed-by: Bjorn Andersson Regards, Bjorn > --- > drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 17 ++++++++++++ > drivers/iommu/arm/arm-smmu/arm-smmu.h | 2 ++ > include/linux/adreno-smmu-priv.h | 31 +++++++++++++++++++++- > 3 files changed, 49 insertions(+), 1 deletion(-) > > diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c > index 98b3a1c2a181..b2e31ea84128 100644 > --- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c > +++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c > @@ -32,6 +32,22 @@ static void qcom_adreno_smmu_write_sctlr(struct arm_smmu_device *smmu, int idx, > arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_SCTLR, reg); > } > > +static void qcom_adreno_smmu_get_fault_info(const void *cookie, > + struct adreno_smmu_fault_info *info) > +{ > + struct arm_smmu_domain *smmu_domain = (void *)cookie; > + struct arm_smmu_cfg *cfg = &smmu_domain->cfg; > + struct arm_smmu_device *smmu = smmu_domain->smmu; > + > + info->fsr = arm_smmu_cb_read(smmu, cfg->cbndx, ARM_SMMU_CB_FSR); > + info->fsynr0 = arm_smmu_cb_read(smmu, cfg->cbndx, ARM_SMMU_CB_FSYNR0); > + info->fsynr1 = arm_smmu_cb_read(smmu, cfg->cbndx, ARM_SMMU_CB_FSYNR1); > + info->far = arm_smmu_cb_readq(smmu, cfg->cbndx, ARM_SMMU_CB_FAR); > + info->cbfrsynra = arm_smmu_gr1_read(smmu, ARM_SMMU_GR1_CBFRSYNRA(cfg->cbndx)); > + info->ttbr0 = arm_smmu_cb_read(smmu, cfg->cbndx, ARM_SMMU_CB_TTBR0); > + info->contextidr = arm_smmu_cb_read(smmu, cfg->cbndx, ARM_SMMU_CB_CONTEXTIDR); > +} > + > #define QCOM_ADRENO_SMMU_GPU_SID 0 > > static bool qcom_adreno_smmu_is_gpu_device(struct device *dev) > @@ -156,6 +172,7 @@ static int qcom_adreno_smmu_init_context(struct arm_smmu_domain *smmu_domain, > priv->cookie = smmu_domain; > priv->get_ttbr1_cfg = qcom_adreno_smmu_get_ttbr1_cfg; > priv->set_ttbr0_cfg = qcom_adreno_smmu_set_ttbr0_cfg; > + priv->get_fault_info = qcom_adreno_smmu_get_fault_info; > > return 0; > } > diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu.h b/drivers/iommu/arm/arm-smmu/arm-smmu.h > index c31a59d35c64..84c21c4b0691 100644 > --- a/drivers/iommu/arm/arm-smmu/arm-smmu.h > +++ b/drivers/iommu/arm/arm-smmu/arm-smmu.h > @@ -224,6 +224,8 @@ enum arm_smmu_cbar_type { > #define ARM_SMMU_CB_FSYNR0 0x68 > #define ARM_SMMU_FSYNR0_WNR BIT(4) > > +#define ARM_SMMU_CB_FSYNR1 0x6c > + > #define ARM_SMMU_CB_S1_TLBIVA 0x600 > #define ARM_SMMU_CB_S1_TLBIASID 0x610 > #define ARM_SMMU_CB_S1_TLBIVAL 0x620 > diff --git a/include/linux/adreno-smmu-priv.h b/include/linux/adreno-smmu-priv.h > index a889f28afb42..53fe32fb9214 100644 > --- a/include/linux/adreno-smmu-priv.h > +++ b/include/linux/adreno-smmu-priv.h > @@ -8,6 +8,32 @@ > > #include > > +/** > + * struct adreno_smmu_fault_info - container for key fault information > + * > + * @far: The faulting IOVA from ARM_SMMU_CB_FAR > + * @ttbr0: The current TTBR0 pagetable from ARM_SMMU_CB_TTBR0 > + * @contextidr: The value of ARM_SMMU_CB_CONTEXTIDR > + * @fsr: The fault status from ARM_SMMU_CB_FSR > + * @fsynr0: The value of FSYNR0 from ARM_SMMU_CB_FSYNR0 > + * @fsynr1: The value of FSYNR1 from ARM_SMMU_CB_FSYNR0 > + * @cbfrsynra: The value of CBFRSYNRA from ARM_SMMU_GR1_CBFRSYNRA(idx) > + * > + * This struct passes back key page fault information to the GPU driver > + * through the get_fault_info function pointer. > + * The GPU driver can use this information to print informative > + * log messages and provide deeper GPU specific insight into the fault. > + */ > +struct adreno_smmu_fault_info { > + u64 far; > + u64 ttbr0; > + u32 contextidr; > + u32 fsr; > + u32 fsynr0; > + u32 fsynr1; > + u32 cbfrsynra; > +}; > + > /** > * struct adreno_smmu_priv - private interface between adreno-smmu and GPU > * > @@ -17,6 +43,8 @@ > * @set_ttbr0_cfg: Set the TTBR0 config for the GPUs context bank. A > * NULL config disables TTBR0 translation, otherwise > * TTBR0 translation is enabled with the specified cfg > + * @get_fault_info: Called by the GPU fault handler to get information about > + * the fault > * > * The GPU driver (drm/msm) and adreno-smmu work together for controlling > * the GPU's SMMU instance. This is by necessity, as the GPU is directly > @@ -31,6 +59,7 @@ struct adreno_smmu_priv { > const void *cookie; > const struct io_pgtable_cfg *(*get_ttbr1_cfg)(const void *cookie); > int (*set_ttbr0_cfg)(const void *cookie, const struct io_pgtable_cfg *cfg); > + void (*get_fault_info)(const void *cookie, struct adreno_smmu_fault_info *info); > }; > > -#endif /* __ADRENO_SMMU_PRIV_H */ > \ No newline at end of file > +#endif /* __ADRENO_SMMU_PRIV_H */ > -- > 2.31.1 > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2A4B6C4743C for ; Mon, 14 Jun 2021 17:30:15 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id E4C3561246 for ; Mon, 14 Jun 2021 17:30:14 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org E4C3561246 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linaro.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 533AE89D7B; Mon, 14 Jun 2021 17:30:14 +0000 (UTC) Received: from mail-oi1-x22a.google.com (mail-oi1-x22a.google.com [IPv6:2607:f8b0:4864:20::22a]) by gabe.freedesktop.org (Postfix) with ESMTPS id 1693489DB5 for ; Mon, 14 Jun 2021 17:30:14 +0000 (UTC) Received: by mail-oi1-x22a.google.com with SMTP id t40so15137809oiw.8 for ; Mon, 14 Jun 2021 10:30:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to; bh=xLux/4m5ofoODBdUbT7Ehl5QrekB6WictYiNsn1mOWI=; b=BmXLqT56g32BvBM3bzR5kCvabeozm5NrpVSpsIpgvkOTPWRPJlxZ/z/D73OSBK/6W5 6A5m0lZLGJQrk0wbOzn8azG01wcz2L7fv3KIn5f+5da/PfQrL2Jj+557OyLbNa9Lqrer 8KztQ1xFxpDOcaY4LfrVezdrtI0n1Y6Elzgs5dh8Hl1F/TueJNJO4giGIFov47dp7kTZ AGxDoJ2L3ig2rYKdAyR0GGF3tq0K5rTrQW3NZH8wS/6twS9QR0yZeHE5iOjmi1EOxiwm upaQMi/vLbzIB1+4Elozh2AyCxcKDl1DyEq3zToBpNm8On3qgzOIKhkII3HppjMv2rnf /qAA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to; bh=xLux/4m5ofoODBdUbT7Ehl5QrekB6WictYiNsn1mOWI=; b=Sy8OAVKLgJBMmg/iBdR4E3uLfroOQ4GlxLizN8mFYk3bewv5b12exgw315LS2aAYti xxnK4z1DNNYBXDyN1KJ1QS3NAZi6XC6ZKxLPzIOftVvCTHVZLN8OdKPcPX4VNC7kb05h L5HzxlaZBvcn5u3VX8GvEpWXMkplfYgccgsQJ2QPCgzaC9iap+Uc+AQr6o/gCHB6nZfu WlD2+PY/bsDMjW4DoZ518PF9i5NBlt5Wj/hnOlB+N4r+mVIJnxE/jKRUYFqtM6FUgK2C zkgWdujwVylmtKTTZG25rdqOkQNTYdRnbBeHc1vpIqQXun7zZ360XjHrkt+DQl7wB1je DNGQ== X-Gm-Message-State: AOAM531HAovOiqlKfIy/jmWPds7Ou42U0N5mUrw/VMJQ4ea/2e4VJW2o OFcDRwpG/3D8WCP4eo+XWGzB/A== X-Google-Smtp-Source: ABdhPJw8j+3e3AKEgROrlKNjzXSDsCtRrFzgE31HIB9XuZeQfTHZGaNm//El0eGHEbYeJRKmO7lkjg== X-Received: by 2002:aca:ac47:: with SMTP id v68mr11196061oie.160.1623691813324; Mon, 14 Jun 2021 10:30:13 -0700 (PDT) Received: from yoga (104-57-184-186.lightspeed.austtx.sbcglobal.net. [104.57.184.186]) by smtp.gmail.com with ESMTPSA id f7sm3169502oot.36.2021.06.14.10.30.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 14 Jun 2021 10:30:12 -0700 (PDT) Date: Mon, 14 Jun 2021 12:30:10 -0500 From: Bjorn Andersson To: Rob Clark Subject: Re: [PATCH v5 2/5] iommu/arm-smmu-qcom: Add an adreno-smmu-priv callback to get pagefault info Message-ID: References: <20210610214431.539029-1-robdclark@gmail.com> <20210610214431.539029-3-robdclark@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20210610214431.539029-3-robdclark@gmail.com> X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Rob Clark , "Isaac J. Manjarres" , Sai Prakash Ranjan , open list , Will Deacon , linux-arm-msm@vger.kernel.org, Joerg Roedel , Jordan Crouse , dri-devel@lists.freedesktop.org, Jordan Crouse , iommu@lists.linux-foundation.org, Krishna Reddy , freedreno@lists.freedesktop.org, "moderated list:ARM SMMU DRIVERS" , Robin Murphy Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" On Thu 10 Jun 16:44 CDT 2021, Rob Clark wrote: > From: Jordan Crouse > > Add a callback in adreno-smmu-priv to read interesting SMMU > registers to provide an opportunity for a richer debug experience > in the GPU driver. > > Signed-off-by: Jordan Crouse > Signed-off-by: Rob Clark I presume this implies that more generic options has been discussed. Regardless, if further conclusions are made in that regard I expect that this could serve as a base for such efforts. Reviewed-by: Bjorn Andersson Regards, Bjorn > --- > drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 17 ++++++++++++ > drivers/iommu/arm/arm-smmu/arm-smmu.h | 2 ++ > include/linux/adreno-smmu-priv.h | 31 +++++++++++++++++++++- > 3 files changed, 49 insertions(+), 1 deletion(-) > > diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c > index 98b3a1c2a181..b2e31ea84128 100644 > --- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c > +++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c > @@ -32,6 +32,22 @@ static void qcom_adreno_smmu_write_sctlr(struct arm_smmu_device *smmu, int idx, > arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_SCTLR, reg); > } > > +static void qcom_adreno_smmu_get_fault_info(const void *cookie, > + struct adreno_smmu_fault_info *info) > +{ > + struct arm_smmu_domain *smmu_domain = (void *)cookie; > + struct arm_smmu_cfg *cfg = &smmu_domain->cfg; > + struct arm_smmu_device *smmu = smmu_domain->smmu; > + > + info->fsr = arm_smmu_cb_read(smmu, cfg->cbndx, ARM_SMMU_CB_FSR); > + info->fsynr0 = arm_smmu_cb_read(smmu, cfg->cbndx, ARM_SMMU_CB_FSYNR0); > + info->fsynr1 = arm_smmu_cb_read(smmu, cfg->cbndx, ARM_SMMU_CB_FSYNR1); > + info->far = arm_smmu_cb_readq(smmu, cfg->cbndx, ARM_SMMU_CB_FAR); > + info->cbfrsynra = arm_smmu_gr1_read(smmu, ARM_SMMU_GR1_CBFRSYNRA(cfg->cbndx)); > + info->ttbr0 = arm_smmu_cb_read(smmu, cfg->cbndx, ARM_SMMU_CB_TTBR0); > + info->contextidr = arm_smmu_cb_read(smmu, cfg->cbndx, ARM_SMMU_CB_CONTEXTIDR); > +} > + > #define QCOM_ADRENO_SMMU_GPU_SID 0 > > static bool qcom_adreno_smmu_is_gpu_device(struct device *dev) > @@ -156,6 +172,7 @@ static int qcom_adreno_smmu_init_context(struct arm_smmu_domain *smmu_domain, > priv->cookie = smmu_domain; > priv->get_ttbr1_cfg = qcom_adreno_smmu_get_ttbr1_cfg; > priv->set_ttbr0_cfg = qcom_adreno_smmu_set_ttbr0_cfg; > + priv->get_fault_info = qcom_adreno_smmu_get_fault_info; > > return 0; > } > diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu.h b/drivers/iommu/arm/arm-smmu/arm-smmu.h > index c31a59d35c64..84c21c4b0691 100644 > --- a/drivers/iommu/arm/arm-smmu/arm-smmu.h > +++ b/drivers/iommu/arm/arm-smmu/arm-smmu.h > @@ -224,6 +224,8 @@ enum arm_smmu_cbar_type { > #define ARM_SMMU_CB_FSYNR0 0x68 > #define ARM_SMMU_FSYNR0_WNR BIT(4) > > +#define ARM_SMMU_CB_FSYNR1 0x6c > + > #define ARM_SMMU_CB_S1_TLBIVA 0x600 > #define ARM_SMMU_CB_S1_TLBIASID 0x610 > #define ARM_SMMU_CB_S1_TLBIVAL 0x620 > diff --git a/include/linux/adreno-smmu-priv.h b/include/linux/adreno-smmu-priv.h > index a889f28afb42..53fe32fb9214 100644 > --- a/include/linux/adreno-smmu-priv.h > +++ b/include/linux/adreno-smmu-priv.h > @@ -8,6 +8,32 @@ > > #include > > +/** > + * struct adreno_smmu_fault_info - container for key fault information > + * > + * @far: The faulting IOVA from ARM_SMMU_CB_FAR > + * @ttbr0: The current TTBR0 pagetable from ARM_SMMU_CB_TTBR0 > + * @contextidr: The value of ARM_SMMU_CB_CONTEXTIDR > + * @fsr: The fault status from ARM_SMMU_CB_FSR > + * @fsynr0: The value of FSYNR0 from ARM_SMMU_CB_FSYNR0 > + * @fsynr1: The value of FSYNR1 from ARM_SMMU_CB_FSYNR0 > + * @cbfrsynra: The value of CBFRSYNRA from ARM_SMMU_GR1_CBFRSYNRA(idx) > + * > + * This struct passes back key page fault information to the GPU driver > + * through the get_fault_info function pointer. > + * The GPU driver can use this information to print informative > + * log messages and provide deeper GPU specific insight into the fault. > + */ > +struct adreno_smmu_fault_info { > + u64 far; > + u64 ttbr0; > + u32 contextidr; > + u32 fsr; > + u32 fsynr0; > + u32 fsynr1; > + u32 cbfrsynra; > +}; > + > /** > * struct adreno_smmu_priv - private interface between adreno-smmu and GPU > * > @@ -17,6 +43,8 @@ > * @set_ttbr0_cfg: Set the TTBR0 config for the GPUs context bank. A > * NULL config disables TTBR0 translation, otherwise > * TTBR0 translation is enabled with the specified cfg > + * @get_fault_info: Called by the GPU fault handler to get information about > + * the fault > * > * The GPU driver (drm/msm) and adreno-smmu work together for controlling > * the GPU's SMMU instance. This is by necessity, as the GPU is directly > @@ -31,6 +59,7 @@ struct adreno_smmu_priv { > const void *cookie; > const struct io_pgtable_cfg *(*get_ttbr1_cfg)(const void *cookie); > int (*set_ttbr0_cfg)(const void *cookie, const struct io_pgtable_cfg *cfg); > + void (*get_fault_info)(const void *cookie, struct adreno_smmu_fault_info *info); > }; > > -#endif /* __ADRENO_SMMU_PRIV_H */ > \ No newline at end of file > +#endif /* __ADRENO_SMMU_PRIV_H */ > -- > 2.31.1 >