From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E827EC4743C for ; Mon, 21 Jun 2021 12:14:22 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 8ADD461042 for ; Mon, 21 Jun 2021 12:14:22 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 8ADD461042 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=ideasonboard.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 2540A89F71; Mon, 21 Jun 2021 12:14:22 +0000 (UTC) Received: from perceval.ideasonboard.com (perceval.ideasonboard.com [IPv6:2001:4b98:dc2:55:216:3eff:fef7:d647]) by gabe.freedesktop.org (Postfix) with ESMTPS id 87FEC89F71 for ; Mon, 21 Jun 2021 12:14:21 +0000 (UTC) Received: from pendragon.ideasonboard.com (62-78-145-57.bb.dnainternet.fi [62.78.145.57]) by perceval.ideasonboard.com (Postfix) with ESMTPSA id B01945A1; Mon, 21 Jun 2021 14:14:18 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ideasonboard.com; s=mail; t=1624277658; bh=+ClJZblBGVPAFwY0Ta7BwECSR+32bJkGg/hx+xJn/cQ=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=uua9KIqHlJZN7EtAoRLgHEoUuKdXLOpVy5+fd9+/ek8tp6IP1UJrpiXJEbrs6soLV ypPseJMOPFBOlHIFtjoQiNgP4xwn3J8Ld+pUz0BQ+B9dYbYMip3OAZg2tZo4/LNPHF xXZ2MBIbMq3fHS/yDfSS8t1o+S/JMGvtV+en9ALQ= Date: Mon, 21 Jun 2021 15:13:52 +0300 From: Laurent Pinchart To: Marek Vasut Subject: Re: [PATCH] drm: mxsfb: Enable recovery on underflow Message-ID: References: <20210620224701.189289-1-marex@denx.de> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline In-Reply-To: <20210620224701.189289-1-marex@denx.de> X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: ch@denx.de, Emil Velikov , Daniel Abrecht , dri-devel@lists.freedesktop.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Hi Marek, Thank you for the patch. On Mon, Jun 21, 2021 at 12:47:01AM +0200, Marek Vasut wrote: > There is some sort of corner case behavior of the controller, > which could rarely be triggered at least on i.MX6SX connected > to 800x480 DPI panel and i.MX8MM connected to DPI->DSI->LVDS > bridged 1920x1080 panel (and likely on other setups too), where > the image on the panel shifts to the right and wraps around. > This happens either when the controller is enabled on boot or > even later during run time. The condition does not correct > itself automatically, i.e. the display image remains shifted. > > It seems this problem is known and is due to sporadic underflows > of the LCDIF FIFO. While the LCDIF IP does have underflow/overflow > IRQs, neither of the IRQs trigger and neither IRQ status bit is > asserted when this condition occurs. > > All known revisions of the LCDIF IP have CTRL1 RECOVER_ON_UNDERFLOW > bit, which is described in the reference manual since i.MX23 as > " > Set this bit to enable the LCDIF block to recover in the next > field/frame if there was an underflow in the current field/frame. > " > Enable this bit to mitigate the sporadic underflows. > > Fixes: 45d59d704080 ("drm: Add new driver for MXSFB controller") > Signed-off-by: Marek Vasut > Cc: Daniel Abrecht > Cc: Emil Velikov > Cc: Laurent Pinchart > Cc: Lucas Stach > Cc: Stefan Agner > --- > drivers/gpu/drm/mxsfb/mxsfb_kms.c | 29 +++++++++++++++++++++++++++++ > drivers/gpu/drm/mxsfb/mxsfb_regs.h | 1 + > 2 files changed, 30 insertions(+) > > diff --git a/drivers/gpu/drm/mxsfb/mxsfb_kms.c b/drivers/gpu/drm/mxsfb/mxsfb_kms.c > index 300e7bab0f43..01e0f525360f 100644 > --- a/drivers/gpu/drm/mxsfb/mxsfb_kms.c > +++ b/drivers/gpu/drm/mxsfb/mxsfb_kms.c > @@ -115,6 +115,35 @@ static void mxsfb_enable_controller(struct mxsfb_drm_private *mxsfb) > reg |= VDCTRL4_SYNC_SIGNALS_ON; > writel(reg, mxsfb->base + LCDC_VDCTRL4); > > + /* > + * Enable recovery on underflow. > + * > + * There is some sort of corner case behavior of the controller, > + * which could rarely be triggered at least on i.MX6SX connected > + * to 800x480 DPI panel and i.MX8MM connected to DPI->DSI->LVDS > + * bridged 1920x1080 panel (and likely on other setups too), where > + * the image on the panel shifts to the right and wraps around. > + * This happens either when the controller is enabled on boot or > + * even later during run time. The condition does not correct > + * itself automatically, i.e. the display image remains shifted. > + * > + * It seems this problem is known and is due to sporadic underflows > + * of the LCDIF FIFO. While the LCDIF IP does have underflow/overflow > + * IRQs, neither of the IRQs trigger and neither IRQ status bit is > + * asserted when this condition occurs. > + * > + * All known revisions of the LCDIF IP have CTRL1 RECOVER_ON_UNDERFLOW > + * bit, which is described in the reference manual since i.MX23 as > + * " > + * Set this bit to enable the LCDIF block to recover in the next > + * field/frame if there was an underflow in the current field/frame. > + * " > + * Enable this bit to mitigate the sporadic underflows. > + */ > + reg = readl(mxsfb->base + LCDC_CTRL1); > + reg |= CTRL1_RECOVER_ON_UNDERFLOW; > + writel(reg, mxsfb->base + LCDC_CTRL1); Looks good to me. Thanks for the detailed explanation. Reviewed-by: Laurent Pinchart > + > writel(CTRL_RUN, mxsfb->base + LCDC_CTRL + REG_SET); > } > > diff --git a/drivers/gpu/drm/mxsfb/mxsfb_regs.h b/drivers/gpu/drm/mxsfb/mxsfb_regs.h > index 55d28a27f912..df90e960f495 100644 > --- a/drivers/gpu/drm/mxsfb/mxsfb_regs.h > +++ b/drivers/gpu/drm/mxsfb/mxsfb_regs.h > @@ -54,6 +54,7 @@ > #define CTRL_DF24 BIT(1) > #define CTRL_RUN BIT(0) > > +#define CTRL1_RECOVER_ON_UNDERFLOW BIT(24) > #define CTRL1_FIFO_CLEAR BIT(21) > #define CTRL1_SET_BYTE_PACKAGING(x) (((x) & 0xf) << 16) > #define CTRL1_GET_BYTE_PACKAGING(x) (((x) >> 16) & 0xf) -- Regards, Laurent Pinchart