From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8A7F3C07E95 for ; Tue, 13 Jul 2021 13:38:26 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 3B5C2611C0 for ; Tue, 13 Jul 2021 13:38:26 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 3B5C2611C0 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=ffwll.ch Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 3CE9189DED; Tue, 13 Jul 2021 13:38:22 +0000 (UTC) Received: from mail-wm1-x32c.google.com (mail-wm1-x32c.google.com [IPv6:2a00:1450:4864:20::32c]) by gabe.freedesktop.org (Postfix) with ESMTPS id 980A089DA6 for ; Tue, 13 Jul 2021 13:38:20 +0000 (UTC) Received: by mail-wm1-x32c.google.com with SMTP id l18-20020a1ced120000b029014c1adff1edso1653891wmh.4 for ; Tue, 13 Jul 2021 06:38:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ffwll.ch; s=google; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to; bh=JXgLaEMV9AycbR+aBsr1GEHEZTKsPIe+O8bYHgn0+8A=; b=No9W2eV0gFGsdgaro083xZsih7wNstPq317G3RZvMpcFHmxf+pyZR97e3sdDZPr5wQ f6MnmfXpXs3IPPIkrYmd/nJSHVq2Hh1s8VHYZ2RiBZM+J1MscUgt3ntRRPyWX3coys6A 55WmXn1nAjqEbJEy0iBM+f3mK82hSB2zmQxCs= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to; bh=JXgLaEMV9AycbR+aBsr1GEHEZTKsPIe+O8bYHgn0+8A=; b=syzWMw7mRYZO31eekNoYJ64QX3wieT7wgtNkizVOD/Z7GD7NHGeeC/ivyS9d/dViBq IKN1T8bKDx75i/ToNLxkcmmaFKkssVU18I0bo+/G3wST0Fpfo1q/TbNn3Z0lK/hqg11I /GEyhqaIrBu56te18BiVlafBjy2Rp0Oxj+jy+B38oHK06cahLLuzoWGa15OAh4KBer4X UY6qARi7K/NNbDE4hLGF/qGT5sa23cwKkdGYtT87k+viag4EEEjGTWSBeZJMy8O7A0uO mdQpfDJGmCiJjYhPqyasJiZvfctQeWsHvZDmAwjhvEH1FEYBjT8nlWC0lXOVsdmDyZdG mWIQ== X-Gm-Message-State: AOAM532Kuq1rdm4qsE5Q60O2D9rrYjR93vCKoVfSf9AgqAg+gexK9HAB ak9I9F75rTuk7IWG0jBSiFJx5Q== X-Google-Smtp-Source: ABdhPJwKGByb0HrM4b/cEyIP5bovAUjTfz49C8V5J0SWHVircUw7X9KjQ7WgW7xM6dnU5pGOBEJrdw== X-Received: by 2002:a1c:9d8f:: with SMTP id g137mr72380wme.13.1626183499233; Tue, 13 Jul 2021 06:38:19 -0700 (PDT) Received: from phenom.ffwll.local ([2a02:168:57f4:0:efd0:b9e5:5ae6:c2fa]) by smtp.gmail.com with ESMTPSA id d24sm2408801wmb.42.2021.07.13.06.38.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 13 Jul 2021 06:38:18 -0700 (PDT) Date: Tue, 13 Jul 2021 15:38:16 +0200 From: Daniel Vetter To: Matthew Auld Message-ID: References: <20210713130431.2392740-1-matthew.auld@intel.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20210713130431.2392740-1-matthew.auld@intel.com> X-Operating-System: Linux phenom 5.10.0-7-amd64 Subject: Re: [Intel-gfx] [PATCH] drm/i915/gtt: drop the page table optimisation X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: dri-devel@lists.freedesktop.org, intel-gfx@lists.freedesktop.org, stable@vger.kernel.org, Chris Wilson Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" On Tue, Jul 13, 2021 at 02:04:31PM +0100, Matthew Auld wrote: > We skip filling out the pt with scratch entries if the va range covers > the entire pt, since we later have to fill it with the PTEs for the > object pages anyway. However this might leave open a small window where > the PTEs don't point to anything valid for the HW to consume. > > When for example using 2M GTT pages this fill_px() showed up as being > quite significant in perf measurements, and ends up being completely > wasted since we ignore the pt and just use the pde directly. > > Anyway, currently we have our PTE construction split between alloc and > insert, which is probably slightly iffy nowadays, since the alloc > doesn't actually allocate anything anymore, instead it just sets up the > page directories and points the PTEs at the scratch page. Later when we > do the insert step we re-program the PTEs again. Better might be to > squash the alloc and insert into a single step, then bringing back this > optimisation(along with some others) should be possible. > > Fixes: 14826673247e ("drm/i915: Only initialize partially filled pagetables") > Signed-off-by: Matthew Auld > Cc: Jon Bloomfield > Cc: Chris Wilson > Cc: Daniel Vetter > Cc: # v4.15+ This is some impressively convoluted code, and I'm scared. But as far as I managed to convince myself, your story here checks out. Problem will be a bit that this code moved around a _lot_ so we'll need a lot of dedicated backports :-( Reviewed-by: Daniel Vetter > --- > drivers/gpu/drm/i915/gt/gen8_ppgtt.c | 5 +---- > 1 file changed, 1 insertion(+), 4 deletions(-) > > diff --git a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c > index 3d02c726c746..6e0e52eeb87a 100644 > --- a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c > +++ b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c > @@ -303,10 +303,7 @@ static void __gen8_ppgtt_alloc(struct i915_address_space * const vm, > __i915_gem_object_pin_pages(pt->base); > i915_gem_object_make_unshrinkable(pt->base); > > - if (lvl || > - gen8_pt_count(*start, end) < I915_PDES || > - intel_vgpu_active(vm->i915)) > - fill_px(pt, vm->scratch[lvl]->encode); > + fill_px(pt, vm->scratch[lvl]->encode); > > spin_lock(&pd->lock); > if (likely(!pd->entry[idx])) { > -- > 2.26.3 > -- Daniel Vetter Software Engineer, Intel Corporation http://blog.ffwll.ch _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id BBEBEC07E96 for ; Tue, 13 Jul 2021 13:38:22 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id C158461175 for ; Tue, 13 Jul 2021 13:38:21 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org C158461175 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=ffwll.ch Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id D168689DA6; Tue, 13 Jul 2021 13:38:20 +0000 (UTC) Received: from mail-wm1-x336.google.com (mail-wm1-x336.google.com [IPv6:2a00:1450:4864:20::336]) by gabe.freedesktop.org (Postfix) with ESMTPS id 995E289DED for ; Tue, 13 Jul 2021 13:38:20 +0000 (UTC) Received: by mail-wm1-x336.google.com with SMTP id b14-20020a1c1b0e0000b02901fc3a62af78so1660140wmb.3 for ; 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Tue, 13 Jul 2021 06:38:19 -0700 (PDT) Received: from phenom.ffwll.local ([2a02:168:57f4:0:efd0:b9e5:5ae6:c2fa]) by smtp.gmail.com with ESMTPSA id d24sm2408801wmb.42.2021.07.13.06.38.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 13 Jul 2021 06:38:18 -0700 (PDT) Date: Tue, 13 Jul 2021 15:38:16 +0200 From: Daniel Vetter To: Matthew Auld Subject: Re: [PATCH] drm/i915/gtt: drop the page table optimisation Message-ID: References: <20210713130431.2392740-1-matthew.auld@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20210713130431.2392740-1-matthew.auld@intel.com> X-Operating-System: Linux phenom 5.10.0-7-amd64 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: dri-devel@lists.freedesktop.org, intel-gfx@lists.freedesktop.org, stable@vger.kernel.org, Jon Bloomfield , Chris Wilson Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" On Tue, Jul 13, 2021 at 02:04:31PM +0100, Matthew Auld wrote: > We skip filling out the pt with scratch entries if the va range covers > the entire pt, since we later have to fill it with the PTEs for the > object pages anyway. However this might leave open a small window where > the PTEs don't point to anything valid for the HW to consume. > > When for example using 2M GTT pages this fill_px() showed up as being > quite significant in perf measurements, and ends up being completely > wasted since we ignore the pt and just use the pde directly. > > Anyway, currently we have our PTE construction split between alloc and > insert, which is probably slightly iffy nowadays, since the alloc > doesn't actually allocate anything anymore, instead it just sets up the > page directories and points the PTEs at the scratch page. Later when we > do the insert step we re-program the PTEs again. Better might be to > squash the alloc and insert into a single step, then bringing back this > optimisation(along with some others) should be possible. > > Fixes: 14826673247e ("drm/i915: Only initialize partially filled pagetables") > Signed-off-by: Matthew Auld > Cc: Jon Bloomfield > Cc: Chris Wilson > Cc: Daniel Vetter > Cc: # v4.15+ This is some impressively convoluted code, and I'm scared. But as far as I managed to convince myself, your story here checks out. Problem will be a bit that this code moved around a _lot_ so we'll need a lot of dedicated backports :-( Reviewed-by: Daniel Vetter > --- > drivers/gpu/drm/i915/gt/gen8_ppgtt.c | 5 +---- > 1 file changed, 1 insertion(+), 4 deletions(-) > > diff --git a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c > index 3d02c726c746..6e0e52eeb87a 100644 > --- a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c > +++ b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c > @@ -303,10 +303,7 @@ static void __gen8_ppgtt_alloc(struct i915_address_space * const vm, > __i915_gem_object_pin_pages(pt->base); > i915_gem_object_make_unshrinkable(pt->base); > > - if (lvl || > - gen8_pt_count(*start, end) < I915_PDES || > - intel_vgpu_active(vm->i915)) > - fill_px(pt, vm->scratch[lvl]->encode); > + fill_px(pt, vm->scratch[lvl]->encode); > > spin_lock(&pd->lock); > if (likely(!pd->entry[idx])) { > -- > 2.26.3 > -- Daniel Vetter Software Engineer, Intel Corporation http://blog.ffwll.ch From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1A969C07E95 for ; Tue, 13 Jul 2021 13:38:22 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id EB3ED611CB for ; Tue, 13 Jul 2021 13:38:21 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236596AbhGMNlL (ORCPT ); Tue, 13 Jul 2021 09:41:11 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60882 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236222AbhGMNlK (ORCPT ); Tue, 13 Jul 2021 09:41:10 -0400 Received: from mail-wm1-x336.google.com (mail-wm1-x336.google.com [IPv6:2a00:1450:4864:20::336]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DE680C0613DD for ; Tue, 13 Jul 2021 06:38:20 -0700 (PDT) Received: by mail-wm1-x336.google.com with SMTP id m11-20020a05600c3b0bb0290228f19cb433so1674890wms.0 for ; Tue, 13 Jul 2021 06:38:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ffwll.ch; s=google; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to; bh=JXgLaEMV9AycbR+aBsr1GEHEZTKsPIe+O8bYHgn0+8A=; b=No9W2eV0gFGsdgaro083xZsih7wNstPq317G3RZvMpcFHmxf+pyZR97e3sdDZPr5wQ f6MnmfXpXs3IPPIkrYmd/nJSHVq2Hh1s8VHYZ2RiBZM+J1MscUgt3ntRRPyWX3coys6A 55WmXn1nAjqEbJEy0iBM+f3mK82hSB2zmQxCs= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to; bh=JXgLaEMV9AycbR+aBsr1GEHEZTKsPIe+O8bYHgn0+8A=; b=NbuCx2WAviDcb4gWLp/XBUel8tNT+qmakodDArip23Fx/qUksdp3lC1vZsVATXq1QS R6LFd6X6/eqpLqg9zWO6oe62t0Hz/dI1zdqBquowzrVT+sOFXuxjrmYNCLr1dLALZd9V hvJYCBvvN5JCt1HQiXc9I/bRAPxtnE6cTdQfEYhLHHdeCnRYOSVUCn+VnGQt6yCSAPaO TYnDWlxzU7AereAwNf2tP8L58Ck/D0ibzKqqYydcgyNzM1fufWKptMl9Ms7fZ8bmukzH ZnabADDT1hcB9eoao+j5E+muESBcgG/36Vv7CMY3+wYKFHuKvPmljW0FG/4LSkwokLix v69Q== X-Gm-Message-State: AOAM531lmxeRPVkXIY1IsfTbNJw4tjq485xv8/hpKPvx0hxz9lnDg4xm 0/muq5WULk967WzG1iJ9ASIR4Q== X-Google-Smtp-Source: ABdhPJwKGByb0HrM4b/cEyIP5bovAUjTfz49C8V5J0SWHVircUw7X9KjQ7WgW7xM6dnU5pGOBEJrdw== X-Received: by 2002:a1c:9d8f:: with SMTP id g137mr72380wme.13.1626183499233; Tue, 13 Jul 2021 06:38:19 -0700 (PDT) Received: from phenom.ffwll.local ([2a02:168:57f4:0:efd0:b9e5:5ae6:c2fa]) by smtp.gmail.com with ESMTPSA id d24sm2408801wmb.42.2021.07.13.06.38.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 13 Jul 2021 06:38:18 -0700 (PDT) Date: Tue, 13 Jul 2021 15:38:16 +0200 From: Daniel Vetter To: Matthew Auld Cc: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org, Jon Bloomfield , Chris Wilson , Daniel Vetter , stable@vger.kernel.org Subject: Re: [PATCH] drm/i915/gtt: drop the page table optimisation Message-ID: References: <20210713130431.2392740-1-matthew.auld@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20210713130431.2392740-1-matthew.auld@intel.com> X-Operating-System: Linux phenom 5.10.0-7-amd64 Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org On Tue, Jul 13, 2021 at 02:04:31PM +0100, Matthew Auld wrote: > We skip filling out the pt with scratch entries if the va range covers > the entire pt, since we later have to fill it with the PTEs for the > object pages anyway. However this might leave open a small window where > the PTEs don't point to anything valid for the HW to consume. > > When for example using 2M GTT pages this fill_px() showed up as being > quite significant in perf measurements, and ends up being completely > wasted since we ignore the pt and just use the pde directly. > > Anyway, currently we have our PTE construction split between alloc and > insert, which is probably slightly iffy nowadays, since the alloc > doesn't actually allocate anything anymore, instead it just sets up the > page directories and points the PTEs at the scratch page. Later when we > do the insert step we re-program the PTEs again. Better might be to > squash the alloc and insert into a single step, then bringing back this > optimisation(along with some others) should be possible. > > Fixes: 14826673247e ("drm/i915: Only initialize partially filled pagetables") > Signed-off-by: Matthew Auld > Cc: Jon Bloomfield > Cc: Chris Wilson > Cc: Daniel Vetter > Cc: # v4.15+ This is some impressively convoluted code, and I'm scared. But as far as I managed to convince myself, your story here checks out. Problem will be a bit that this code moved around a _lot_ so we'll need a lot of dedicated backports :-( Reviewed-by: Daniel Vetter > --- > drivers/gpu/drm/i915/gt/gen8_ppgtt.c | 5 +---- > 1 file changed, 1 insertion(+), 4 deletions(-) > > diff --git a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c > index 3d02c726c746..6e0e52eeb87a 100644 > --- a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c > +++ b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c > @@ -303,10 +303,7 @@ static void __gen8_ppgtt_alloc(struct i915_address_space * const vm, > __i915_gem_object_pin_pages(pt->base); > i915_gem_object_make_unshrinkable(pt->base); > > - if (lvl || > - gen8_pt_count(*start, end) < I915_PDES || > - intel_vgpu_active(vm->i915)) > - fill_px(pt, vm->scratch[lvl]->encode); > + fill_px(pt, vm->scratch[lvl]->encode); > > spin_lock(&pd->lock); > if (likely(!pd->entry[idx])) { > -- > 2.26.3 > -- Daniel Vetter Software Engineer, Intel Corporation http://blog.ffwll.ch