From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-0.7 required=3.0 tests=BAYES_00,DKIM_ADSP_CUSTOM_MED, FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM,HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 61479C07E96 for ; Tue, 6 Jul 2021 16:35:25 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 3DFFC61C3C for ; Tue, 6 Jul 2021 16:35:25 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230033AbhGFQiC (ORCPT ); Tue, 6 Jul 2021 12:38:02 -0400 Received: from mga18.intel.com ([134.134.136.126]:3146 "EHLO mga18.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230108AbhGFQiC (ORCPT ); Tue, 6 Jul 2021 12:38:02 -0400 X-IronPort-AV: E=McAfee;i="6200,9189,10037"; a="196432237" X-IronPort-AV: E=Sophos;i="5.83,328,1616482800"; d="scan'208";a="196432237" Received: from orsmga002.jf.intel.com ([10.7.209.21]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Jul 2021 09:35:15 -0700 X-IronPort-AV: E=Sophos;i="5.83,328,1616482800"; d="scan'208";a="427644221" Received: from smile.fi.intel.com (HELO smile) ([10.237.68.40]) by orsmga002-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Jul 2021 09:35:13 -0700 Received: from andy by smile with local (Exim 4.94.2) (envelope-from ) id 1m0o2O-009UkV-Qc; Tue, 06 Jul 2021 19:35:08 +0300 Date: Tue, 6 Jul 2021 19:35:08 +0300 From: Andy Shevchenko To: Hans de Goede Cc: "Rafael J . Wysocki" , Len Brown , Andy Shevchenko , Mika Westerberg , linux-acpi@vger.kernel.org Subject: Re: [PATCH v2 2/2] ACPI / PMIC: XPower: optimize MIPI PMIQ sequence I2C-bus accesses Message-ID: References: <20210706160923.20273-1-hdegoede@redhat.com> <20210706160923.20273-2-hdegoede@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20210706160923.20273-2-hdegoede@redhat.com> Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo Precedence: bulk List-ID: X-Mailing-List: linux-acpi@vger.kernel.org On Tue, Jul 06, 2021 at 06:09:23PM +0200, Hans de Goede wrote: > The I2C-bus to the XPower AXP288 is shared between the Linux kernel and > the SoCs P-Unit. The P-Unit has a semaphore which the kernel must "lock" > before it may use the bus and while the kernel holds the semaphore the CPU > and GPU power-states must not be changed otherwise the system will freeze. > > This is a complex process, which is quite expensive. This is all done by > iosf_mbi_block_punit_i2c_access(). To ensure that no unguarded I2C-bus > accesses happen, iosf_mbi_block_punit_i2c_access() gets called by the > I2C-bus-driver for every I2C transfer. Because this is so expensive it > is allowed to call iosf_mbi_block_punit_i2c_access() in a nested > fashion, so that higher-level code which does multiple I2C-transfers can > call it once for a group of transfers, turning the calls done by the > I2C-bus-driver into no-ops. > > The default exec_mipi_pmic_seq_element implementation from > drivers/acpi/pmic/intel_pmic.c does a regmap_update_bits() call and > the involved registers are typically marked as volatile in the regmap, > so this leads to 2 I2C-bus accesses. > > Add a XPower AXP288 specific implementation of exec_mipi_pmic_seq_element > which calls iosf_mbi_block_punit_i2c_access() calls before the > regmap_update_bits() call to avoid having to do the whole expensive > acquire P-Unit semaphore dance twice. ... The idea for the further improvement > + if (i2c_address != 0x34) { > + pr_err("%s: Unexpected i2c-addr: 0x%02x (reg-addr 0x%x value 0x%x mask 0x%x)\n", > + __func__, i2c_address, reg_address, value, mask); > + return -ENXIO; > + } We have this in intel_pmic.c. Can we reorganize the code the way we will have this check solely in the intel_pmic.c? -- With Best Regards, Andy Shevchenko