From: Andrew Lunn <andrew@lunn.ch>
To: Russell King <rmk+kernel@armlinux.org.uk>
Cc: Heiner Kallweit <hkallweit1@gmail.com>,
"David S. Miller" <davem@davemloft.net>,
netdev@vger.kernel.org, Marek Beh__n <kabel@kernel.org>,
Jakub Kicinski <kuba@kernel.org>
Subject: Re: [PATCH RFC net-next] net: phy: marvell10g: add downshift tunable support
Date: Tue, 20 Jul 2021 16:28:12 +0200 [thread overview]
Message-ID: <YPbdfBqjgHzM+6+Z@lunn.ch> (raw)
In-Reply-To: <E1m5pwy-0003uX-Pf@rmk-PC.armlinux.org.uk>
> +static int mv3310_set_downshift(struct phy_device *phydev, u8 ds)
> +{
> + struct mv3310_priv *priv = dev_get_drvdata(&phydev->mdio.dev);
> + u16 val;
> + int err;
> +
> + /* Fails to downshift with v0.3.5.0 and earlier */
> + if (priv->firmware_ver < MV_VERSION(0,3,5,0))
> + return -EOPNOTSUPP;
> +
> + if (ds == DOWNSHIFT_DEV_DISABLE)
> + return phy_clear_bits_mmd(phydev, MDIO_MMD_PCS, MV_PCS_DSC1,
> + MV_PCS_DSC1_ENABLE);
> +
> + /* FIXME: The default is disabled, so should we disable? */
> + if (ds == DOWNSHIFT_DEV_DEFAULT_COUNT)
> + ds = 2;
Interesting question.
It is a useful feature, so i would enable it by default.
Is it possible to read the actual speed via some vendor register? The
phy-core might then give a warning, but it is 50/50 since the link
peer might perform the downshift.
Andrew
next prev parent reply other threads:[~2021-07-20 14:39 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-07-20 13:38 [PATCH RFC net-next] net: phy: marvell10g: add downshift tunable support Russell King
2021-07-20 14:28 ` Andrew Lunn [this message]
2021-07-20 14:30 ` Russell King (Oracle)
2021-07-20 15:04 ` Marek Behún
2021-07-20 17:14 ` Russell King (Oracle)
2021-07-20 17:32 ` Marek Behún
2021-07-20 17:39 ` Russell King (Oracle)
2021-07-20 17:50 ` Marek Behún
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