From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6B725C4338F for ; Tue, 10 Aug 2021 04:28:15 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id D09126101D for ; Tue, 10 Aug 2021 04:28:14 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org D09126101D Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=gibson.dropbear.id.au Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=nongnu.org Received: from localhost ([::1]:35390 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mDJN7-0007tq-Rp for qemu-devel@archiver.kernel.org; Tue, 10 Aug 2021 00:28:13 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:53010) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mDJEJ-0000gz-0q; Tue, 10 Aug 2021 00:19:07 -0400 Received: from ozlabs.org ([2401:3900:2:1::2]:42871) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mDJEH-0002XF-2v; Tue, 10 Aug 2021 00:19:06 -0400 Received: by ozlabs.org (Postfix, from userid 1007) id 4GkKSX467Tz9tT8; Tue, 10 Aug 2021 14:18:19 +1000 (AEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gibson.dropbear.id.au; s=201602; t=1628569100; bh=XPf3jT3M5KV7BuNFWxEZE0sSaxCU2nBJ+GIFoLHOstg=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=Ta0E4pdDYAdz8ih4gn+5TmV7S5FrXm+yxQzNqNvyIb6VRST7LPyp90uPy1NTa5NBm AtgzLlk/UfxWiZHkerEQze3SXdaKvCqsy52jB51WYyaNqeHsGfCxaKS4zTm60Peq4v HKjn8koLxw4iqvXqvBZO5J7B32EZOXw8vi3ynXeY= Date: Tue, 10 Aug 2021 14:13:16 +1000 From: David Gibson To: Daniel Henrique Barboza Subject: Re: [PATCH 16/19] target/ppc/pmu_book3s_helper: adding 0xFA event Message-ID: References: <20210809131057.1694145-1-danielhb413@gmail.com> <20210809131057.1694145-17-danielhb413@gmail.com> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="Yg4z4DGZZTqNDrb1" Content-Disposition: inline In-Reply-To: <20210809131057.1694145-17-danielhb413@gmail.com> Received-SPF: pass client-ip=2401:3900:2:1::2; envelope-from=dgibson@ozlabs.org; helo=ozlabs.org X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, HEADER_FROM_DIFFERENT_DOMAINS=0.248, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: gustavo.romero@linaro.org, clg@kaod.org, qemu-ppc@nongnu.org, qemu-devel@nongnu.org, groug@kaod.org Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" --Yg4z4DGZZTqNDrb1 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Mon, Aug 09, 2021 at 10:10:54AM -0300, Daniel Henrique Barboza wrote: > The PowerISA 3.1 defines the 0xFA event as instructions completed when > the thread's CTRL register is set. Some EBB powerpc kernel tests use > this event to exercise both the PMU and the EBB support. Couldn't you implement this more accurately by snapshotting the count at each CTRL write, and either adding the delta to the PMC or not depending on the previous CTRL value? > We don't have a way at this moment to tell whether an instruction was > completed under those conditions. What we can do is to make it > equivalent to the existing PM_INST_COMPL event that counts all > instructions completed. For our current purposes with the PMU support > this is enough. >=20 > Signed-off-by: Daniel Henrique Barboza > --- > target/ppc/pmu_book3s_helper.c | 14 ++++++++++++++ > 1 file changed, 14 insertions(+) >=20 > diff --git a/target/ppc/pmu_book3s_helper.c b/target/ppc/pmu_book3s_helpe= r.c > index c5c5ab38c9..388263688b 100644 > --- a/target/ppc/pmu_book3s_helper.c > +++ b/target/ppc/pmu_book3s_helper.c > @@ -52,6 +52,20 @@ static uint8_t get_PMC_event(CPUPPCState *env, int spr= n) > break; > case SPR_POWER_PMC4: > event =3D MMCR1_PMC4SEL & env->spr[SPR_POWER_MMCR1]; > + > + /* > + * Event 0xFA for PMC4SEL is described as follows in > + * PowerISA v3.1: > + * > + * "The thread has completed an instruction when the RUN bit of > + * the thread=E2=80=99s CTRL register contained 1" > + * > + * Our closest equivalent for this event at this moment is plain > + * INST_CMPL (event 0x2) > + */ > + if (event =3D=3D 0xFA) { > + event =3D 0x2; > + } > break; > case SPR_POWER_PMC5: > event =3D 0x2; --=20 David Gibson | I'll have my music baroque, and my code david AT gibson.dropbear.id.au | minimalist, thank you. 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