From: David Gibson <david@gibson.dropbear.id.au>
To: "Philippe Mathieu-Daudé" <f4bug@amsat.org>
Cc: qemu-devel@nongnu.org, thuth@redhat.com, qemu-ppc@nongnu.org,
"Cédric Le Goater" <clg@kaod.org>, "Greg Kurz" <groug@kaod.org>
Subject: Re: [PATCH] xive: Remove extra '0x' prefix in trace events
Date: Tue, 10 Aug 2021 10:56:31 +1000 [thread overview]
Message-ID: <YRHOv3siLEqQuSBB@yekko> (raw)
In-Reply-To: <e546f365-b941-ccda-8ba9-24aadb12da3b@amsat.org>
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On Mon, Aug 09, 2021 at 11:39:49AM +0200, Philippe Mathieu-Daudé wrote:
> On 8/9/21 10:52 AM, Cédric Le Goater wrote:
> > Cc: thuth@redhat.com
> > Fixes: 4e960974d4ee ("xive: Add trace events")
> > Resolves: https://gitlab.com/qemu-project/qemu/-/issues/519
> > Signed-off-by: Cédric Le Goater <clg@kaod.org>
> > ---
> > hw/intc/trace-events | 10 +++++-----
> > 1 file changed, 5 insertions(+), 5 deletions(-)
> >
> > diff --git a/hw/intc/trace-events b/hw/intc/trace-events
> > index e56e7dd3b667..6a17d38998d9 100644
> > --- a/hw/intc/trace-events
> > +++ b/hw/intc/trace-events
> > @@ -219,14 +219,14 @@ kvm_xive_source_reset(uint32_t srcno) "IRQ 0x%x"
> > xive_tctx_accept(uint32_t index, uint8_t ring, uint8_t ipb, uint8_t pipr, uint8_t cppr, uint8_t nsr) "target=%d ring=0x%x IBP=0x%02x PIPR=0x%02x CPPR=0x%02x NSR=0x%02x ACK"
> > xive_tctx_notify(uint32_t index, uint8_t ring, uint8_t ipb, uint8_t pipr, uint8_t cppr, uint8_t nsr) "target=%d ring=0x%x IBP=0x%02x PIPR=0x%02x CPPR=0x%02x NSR=0x%02x raise !"
> > xive_tctx_set_cppr(uint32_t index, uint8_t ring, uint8_t ipb, uint8_t pipr, uint8_t cppr, uint8_t nsr) "target=%d ring=0x%x IBP=0x%02x PIPR=0x%02x new CPPR=0x%02x NSR=0x%02x"
> > -xive_source_esb_read(uint64_t addr, uint32_t srcno, uint64_t value) "@0x0x%"PRIx64" IRQ 0x%x val=0x0x%"PRIx64
> > -xive_source_esb_write(uint64_t addr, uint32_t srcno, uint64_t value) "@0x0x%"PRIx64" IRQ 0x%x val=0x0x%"PRIx64
> > +xive_source_esb_read(uint64_t addr, uint32_t srcno, uint64_t value) "@0x%"PRIx64" IRQ 0x%x val=0x%"PRIx64
> > +xive_source_esb_write(uint64_t addr, uint32_t srcno, uint64_t value) "@0x%"PRIx64" IRQ 0x%x val=0x%"PRIx64
> > xive_router_end_notify(uint8_t end_blk, uint32_t end_idx, uint32_t end_data) "END 0x%02x/0x%04x -> enqueue 0x%08x"
> > xive_router_end_escalate(uint8_t end_blk, uint32_t end_idx, uint8_t esc_blk, uint32_t esc_idx, uint32_t end_data) "END 0x%02x/0x%04x -> escalate END 0x%02x/0x%04x data 0x%08x"
> > -xive_tctx_tm_write(uint64_t offset, unsigned int size, uint64_t value) "@0x0x%"PRIx64" sz=%d val=0x%" PRIx64
> > -xive_tctx_tm_read(uint64_t offset, unsigned int size, uint64_t value) "@0x0x%"PRIx64" sz=%d val=0x%" PRIx64
> > +xive_tctx_tm_write(uint64_t offset, unsigned int size, uint64_t value) "@0x%"PRIx64" sz=%d val=0x%" PRIx64
> > +xive_tctx_tm_read(uint64_t offset, unsigned int size, uint64_t value) "@0x%"PRIx64" sz=%d val=0x%" PRIx64
> > xive_presenter_notify(uint8_t nvt_blk, uint32_t nvt_idx, uint8_t ring) "found NVT 0x%x/0x%x ring=0x%x"
> > -xive_end_source_read(uint8_t end_blk, uint32_t end_idx, uint64_t addr) "END 0x%x/0x%x @0x0x%"PRIx64
> > +xive_end_source_read(uint8_t end_blk, uint32_t end_idx, uint64_t addr) "END 0x%x/0x%x @0x%"PRIx64
> >
> > # pnv_xive.c
> > pnv_xive_ic_hw_trigger(uint64_t addr, uint64_t val) "@0x%"PRIx64" val=0x%"PRIx64
> >
>
> Acceptable for 6.1 IMHO.
Acceptable for, but also not vital for. I've applied this to
ppc-for-6.1, but I'll probably only bother sending a PR if some more
crucial fixes come along.
>
> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
>
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
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next prev parent reply other threads:[~2021-08-10 1:02 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-08-09 8:52 [PATCH] xive: Remove extra '0x' prefix in trace events Cédric Le Goater
2021-08-09 9:39 ` Philippe Mathieu-Daudé
2021-08-10 0:56 ` David Gibson [this message]
2021-08-10 5:03 ` Philippe Mathieu-Daudé
2021-08-09 9:42 ` Laurent Vivier
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