From: Sean Christopherson <seanjc@google.com>
To: Joerg Roedel <joro@8bytes.org>
Cc: Paolo Bonzini <pbonzini@redhat.com>,
Vitaly Kuznetsov <vkuznets@redhat.com>,
Wanpeng Li <wanpengli@tencent.com>,
Jim Mattson <jmattson@google.com>,
Brijesh Singh <brijesh.singh@amd.com>,
Tom Lendacky <thomas.lendacky@amd.com>,
kvm@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-coco@lists.linux.dev, Joerg Roedel <jroedel@suse.de>
Subject: Re: [PATCH v2 1/4] KVM: SVM: Get rid of *ghcb_msr_bits() functions
Date: Wed, 1 Sep 2021 21:12:10 +0000 [thread overview]
Message-ID: <YS/sqmgbS6ACRfSD@google.com> (raw)
In-Reply-To: <20210722115245.16084-2-joro@8bytes.org>
On Thu, Jul 22, 2021, Joerg Roedel wrote:
> From: Joerg Roedel <jroedel@suse.de>
>
> Replace the get function with macros and the set function with
> hypercall specific setters. This will avoid preserving any previous
> bits in the GHCB-MSR and improved code readability.
>
> Suggested-by: Sean Christopherson <seanjc@google.com>
> Signed-off-by: Joerg Roedel <jroedel@suse.de>
> ---
> arch/x86/include/asm/sev-common.h | 9 +++++++
> arch/x86/kvm/svm/sev.c | 41 +++++++++++--------------------
> 2 files changed, 24 insertions(+), 26 deletions(-)
>
> diff --git a/arch/x86/include/asm/sev-common.h b/arch/x86/include/asm/sev-common.h
> index 2cef6c5a52c2..8540972cad04 100644
> --- a/arch/x86/include/asm/sev-common.h
> +++ b/arch/x86/include/asm/sev-common.h
> @@ -50,6 +50,10 @@
> (GHCB_MSR_CPUID_REQ | \
> (((unsigned long)reg & GHCB_MSR_CPUID_REG_MASK) << GHCB_MSR_CPUID_REG_POS) | \
> (((unsigned long)fn) << GHCB_MSR_CPUID_FUNC_POS))
> +#define GHCB_MSR_CPUID_FN(msr) \
> + (((msr) >> GHCB_MSR_CPUID_FUNC_POS) & GHCB_MSR_CPUID_FUNC_MASK)
> +#define GHCB_MSR_CPUID_REG(msr) \
> + (((msr) >> GHCB_MSR_CPUID_REG_POS) & GHCB_MSR_CPUID_REG_MASK)
>
> /* AP Reset Hold */
> #define GHCB_MSR_AP_RESET_HOLD_REQ 0x006
> @@ -67,6 +71,11 @@
> #define GHCB_SEV_TERM_REASON(reason_set, reason_val) \
> (((((u64)reason_set) & GHCB_MSR_TERM_REASON_SET_MASK) << GHCB_MSR_TERM_REASON_SET_POS) | \
> ((((u64)reason_val) & GHCB_MSR_TERM_REASON_MASK) << GHCB_MSR_TERM_REASON_POS))
> +#define GHCB_MSR_TERM_REASON_SET(msr) \
> + (((msr) >> GHCB_MSR_TERM_REASON_SET_POS) & GHCB_MSR_TERM_REASON_SET_MASK)
> +#define GHCB_MSR_TERM_REASON(msr) \
> + (((msr) >> GHCB_MSR_TERM_REASON_POS) & GHCB_MSR_TERM_REASON_MASK)
> +
>
> #define GHCB_SEV_ES_REASON_GENERAL_REQUEST 0
> #define GHCB_SEV_ES_REASON_PROTOCOL_UNSUPPORTED 1
> diff --git a/arch/x86/kvm/svm/sev.c b/arch/x86/kvm/svm/sev.c
> index 6710d9ee2e4b..d7b3557b8dbb 100644
> --- a/arch/x86/kvm/svm/sev.c
> +++ b/arch/x86/kvm/svm/sev.c
> @@ -2342,16 +2342,15 @@ static bool setup_vmgexit_scratch(struct vcpu_svm *svm, bool sync, u64 len)
> return true;
> }
>
> -static void set_ghcb_msr_bits(struct vcpu_svm *svm, u64 value, u64 mask,
> - unsigned int pos)
> +static void set_ghcb_msr_cpuid_resp(struct vcpu_svm *svm, u64 reg, u64 value)
> {
> - svm->vmcb->control.ghcb_gpa &= ~(mask << pos);
> - svm->vmcb->control.ghcb_gpa |= (value & mask) << pos;
> -}
> + u64 msr;
>
> -static u64 get_ghcb_msr_bits(struct vcpu_svm *svm, u64 mask, unsigned int pos)
> -{
> - return (svm->vmcb->control.ghcb_gpa >> pos) & mask;
> + msr = GHCB_MSR_CPUID_RESP;
> + msr |= (reg & GHCB_MSR_CPUID_REG_MASK) << GHCB_MSR_CPUID_REG_POS;
> + msr |= (value & GHCB_MSR_CPUID_VALUE_MASK) << GHCB_MSR_CPUID_VALUE_POS;
> +
> + svm->vmcb->control.ghcb_gpa = msr;
I would rather have the get/set pairs be roughly symmetric, i.e. both functions
or both macros, and both work on svm->vmcb->control.ghcb_gpa or both be purely
functional (that may not be the correct word).
I don't have a strong preference on function vs. macro. But for the second one,
my preference would be to have the helper generate the value as opposed to taken
and filling a pointer, e.g. to yield something like:
cpuid_reg = GHCB_MSR_CPUID_REG(control->ghcb_gpa);
if (cpuid_reg == 0)
cpuid_value = vcpu->arch.regs[VCPU_REGS_RAX];
else if (cpuid_reg == 1)
cpuid_value = vcpu->arch.regs[VCPU_REGS_RBX];
else if (cpuid_reg == 2)
cpuid_value = vcpu->arch.regs[VCPU_REGS_RCX];
else
cpuid_value = vcpu->arch.regs[VCPU_REGS_RDX];
control->ghcb_gpa = MAKE_GHCB_MSR_RESP(cpuid_reg, cpuid_value);
The advantage is that it's obvious from the code that control->ghcb_gpa is being
read _and_ written.
> case GHCB_MSR_TERM_REQ: {
> u64 reason_set, reason_code;
>
> - reason_set = get_ghcb_msr_bits(svm,
> - GHCB_MSR_TERM_REASON_SET_MASK,
> - GHCB_MSR_TERM_REASON_SET_POS);
> - reason_code = get_ghcb_msr_bits(svm,
> - GHCB_MSR_TERM_REASON_MASK,
> - GHCB_MSR_TERM_REASON_POS);
> + reason_set = GHCB_MSR_TERM_REASON_SET(control->ghcb_gpa);
> + reason_code = GHCB_MSR_TERM_REASON(control->ghcb_gpa);
> +
> pr_info("SEV-ES guest requested termination: %#llx:%#llx\n",
> reason_set, reason_code);
> +
> fallthrough;
Not related to this patch, but why use fallthrough and more importantly, why is
this an -EINVAL return? Why wouldn't KVM forward the request to userspace instead
of returning an opaque -EINVAL?
> }
> default:
> --
> 2.31.1
>
next prev parent reply other threads:[~2021-09-01 21:12 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-07-22 11:52 [PATCH v2 0/4] KVM: SVM: Add initial GHCB protocol version 2 support Joerg Roedel
2021-07-22 11:52 ` [PATCH v2 1/4] KVM: SVM: Get rid of *ghcb_msr_bits() functions Joerg Roedel
2021-09-01 21:12 ` Sean Christopherson [this message]
2021-09-01 21:31 ` Sean Christopherson
2021-09-09 13:22 ` Joerg Roedel
2021-09-09 13:32 ` Joerg Roedel
2021-09-20 16:10 ` Sean Christopherson
2021-07-22 11:52 ` [PATCH v2 2/4] KVM: SVM: Add support to handle AP reset MSR protocol Joerg Roedel
2021-09-01 21:45 ` Sean Christopherson
2021-07-22 11:52 ` [PATCH v2 3/4] KVM: SVM: Add support for Hypervisor Feature support " Joerg Roedel
2021-07-22 12:01 ` [PATCH v2.1 " Joerg Roedel
2021-09-01 22:41 ` Sean Christopherson
2021-07-22 11:52 ` [PATCH v2 4/4] KVM: SVM: Increase supported GHCB protocol version Joerg Roedel
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