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[34.68.225.194]) by smtp.gmail.com with ESMTPSA id 7sm425362ilx.16.2021.09.01.14.28.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 Sep 2021 14:28:31 -0700 (PDT) Date: Wed, 1 Sep 2021 21:28:28 +0000 From: Oliver Upton To: Raghavendra Rao Ananta Subject: Re: [PATCH v3 02/12] KVM: arm64: selftests: Add write_sysreg_s and read_sysreg_s Message-ID: References: <20210901211412.4171835-1-rananta@google.com> <20210901211412.4171835-3-rananta@google.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20210901211412.4171835-3-rananta@google.com> Cc: kvm@vger.kernel.org, Will Deacon , Catalin Marinas , Peter Shier , linux-kernel@vger.kernel.org, Marc Zyngier , Paolo Bonzini , kvmarm@lists.cs.columbia.edu, linux-arm-kernel@lists.infradead.org X-BeenThere: kvmarm@lists.cs.columbia.edu X-Mailman-Version: 2.1.14 Precedence: list List-Id: Where KVM/ARM decisions are made List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Errors-To: kvmarm-bounces@lists.cs.columbia.edu Sender: kvmarm-bounces@lists.cs.columbia.edu On Wed, Sep 01, 2021 at 09:14:02PM +0000, Raghavendra Rao Ananta wrote: > For register names that are unsupported by the assembler or the ones > without architectural names, add the macros write_sysreg_s and > read_sysreg_s to support them. > > The functionality is derived from kvm-unit-tests and kernel's > arch/arm64/include/asm/sysreg.h. > > Signed-off-by: Raghavendra Rao Ananta Would it be possible to just include ? See tools/arch/arm64/include/asm/sysreg.h > --- > .../selftests/kvm/include/aarch64/processor.h | 61 +++++++++++++++++++ > 1 file changed, 61 insertions(+) > > diff --git a/tools/testing/selftests/kvm/include/aarch64/processor.h b/tools/testing/selftests/kvm/include/aarch64/processor.h > index 3cbaf5c1e26b..082cc97ad8d3 100644 > --- a/tools/testing/selftests/kvm/include/aarch64/processor.h > +++ b/tools/testing/selftests/kvm/include/aarch64/processor.h > @@ -118,6 +118,67 @@ void vm_install_exception_handler(struct kvm_vm *vm, > void vm_install_sync_handler(struct kvm_vm *vm, > int vector, int ec, handler_fn handler); > > +/* > + * ARMv8 ARM reserves the following encoding for system registers: > + * (Ref: ARMv8 ARM, Section: "System instruction class encoding overview", > + * C5.2, version:ARM DDI 0487A.f) > + * [20-19] : Op0 > + * [18-16] : Op1 > + * [15-12] : CRn > + * [11-8] : CRm > + * [7-5] : Op2 > + */ > +#define Op0_shift 19 > +#define Op0_mask 0x3 > +#define Op1_shift 16 > +#define Op1_mask 0x7 > +#define CRn_shift 12 > +#define CRn_mask 0xf > +#define CRm_shift 8 > +#define CRm_mask 0xf > +#define Op2_shift 5 > +#define Op2_mask 0x7 > + > +/* > + * When accessed from guests, the ARM64_SYS_REG() doesn't work since it > + * generates a different encoding for additional KVM processing, and is > + * only suitable for userspace to access the register via ioctls. > + * Hence, define a 'pure' sys_reg() here to generate the encodings as per spec. > + */ > +#define sys_reg(op0, op1, crn, crm, op2) \ > + (((op0) << Op0_shift) | ((op1) << Op1_shift) | \ > + ((crn) << CRn_shift) | ((crm) << CRm_shift) | \ > + ((op2) << Op2_shift)) > + > +asm( > +" .irp num,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30\n" > +" .equ .L__reg_num_x\\num, \\num\n" > +" .endr\n" > +" .equ .L__reg_num_xzr, 31\n" > +"\n" > +" .macro mrs_s, rt, sreg\n" > +" .inst 0xd5200000|(\\sreg)|(.L__reg_num_\\rt)\n" > +" .endm\n" > +"\n" > +" .macro msr_s, sreg, rt\n" > +" .inst 0xd5000000|(\\sreg)|(.L__reg_num_\\rt)\n" > +" .endm\n" > +); > + > +/* > + * read_sysreg_s() and write_sysreg_s()'s 'reg' has to be encoded via sys_reg() > + */ > +#define read_sysreg_s(reg) ({ \ > + u64 __val; \ > + asm volatile("mrs_s %0, "__stringify(reg) : "=r" (__val)); \ > + __val; \ > +}) > + > +#define write_sysreg_s(reg, val) do { \ > + u64 __val = (u64)val; \ > + asm volatile("msr_s "__stringify(reg) ", %x0" : : "rZ" (__val));\ > +} while (0) > + > #define write_sysreg(reg, val) \ > ({ \ > u64 __val = (u64)(val); \ > -- > 2.33.0.153.gba50c8fa24-goog > _______________________________________________ kvmarm mailing list kvmarm@lists.cs.columbia.edu https://lists.cs.columbia.edu/mailman/listinfo/kvmarm From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-14.1 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_ADSP_CUSTOM_MED,DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D7B21C432BE for ; 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[34.68.225.194]) by smtp.gmail.com with ESMTPSA id 7sm425362ilx.16.2021.09.01.14.28.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 Sep 2021 14:28:31 -0700 (PDT) Date: Wed, 1 Sep 2021 21:28:28 +0000 From: Oliver Upton To: Raghavendra Rao Ananta Cc: Paolo Bonzini , Marc Zyngier , James Morse , Alexandru Elisei , Suzuki K Poulose , Catalin Marinas , Will Deacon , Peter Shier , Ricardo Koller , Reiji Watanabe , Jing Zhang , linux-arm-kernel@lists.infradead.org, kvmarm@lists.cs.columbia.edu, linux-kernel@vger.kernel.org, kvm@vger.kernel.org Subject: Re: [PATCH v3 02/12] KVM: arm64: selftests: Add write_sysreg_s and read_sysreg_s Message-ID: References: <20210901211412.4171835-1-rananta@google.com> <20210901211412.4171835-3-rananta@google.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20210901211412.4171835-3-rananta@google.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210901_142833_490182_10514623 X-CRM114-Status: GOOD ( 23.44 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Wed, Sep 01, 2021 at 09:14:02PM +0000, Raghavendra Rao Ananta wrote: > For register names that are unsupported by the assembler or the ones > without architectural names, add the macros write_sysreg_s and > read_sysreg_s to support them. > > The functionality is derived from kvm-unit-tests and kernel's > arch/arm64/include/asm/sysreg.h. > > Signed-off-by: Raghavendra Rao Ananta Would it be possible to just include ? See tools/arch/arm64/include/asm/sysreg.h > --- > .../selftests/kvm/include/aarch64/processor.h | 61 +++++++++++++++++++ > 1 file changed, 61 insertions(+) > > diff --git a/tools/testing/selftests/kvm/include/aarch64/processor.h b/tools/testing/selftests/kvm/include/aarch64/processor.h > index 3cbaf5c1e26b..082cc97ad8d3 100644 > --- a/tools/testing/selftests/kvm/include/aarch64/processor.h > +++ b/tools/testing/selftests/kvm/include/aarch64/processor.h > @@ -118,6 +118,67 @@ void vm_install_exception_handler(struct kvm_vm *vm, > void vm_install_sync_handler(struct kvm_vm *vm, > int vector, int ec, handler_fn handler); > > +/* > + * ARMv8 ARM reserves the following encoding for system registers: > + * (Ref: ARMv8 ARM, Section: "System instruction class encoding overview", > + * C5.2, version:ARM DDI 0487A.f) > + * [20-19] : Op0 > + * [18-16] : Op1 > + * [15-12] : CRn > + * [11-8] : CRm > + * [7-5] : Op2 > + */ > +#define Op0_shift 19 > +#define Op0_mask 0x3 > +#define Op1_shift 16 > +#define Op1_mask 0x7 > +#define CRn_shift 12 > +#define CRn_mask 0xf > +#define CRm_shift 8 > +#define CRm_mask 0xf > +#define Op2_shift 5 > +#define Op2_mask 0x7 > + > +/* > + * When accessed from guests, the ARM64_SYS_REG() doesn't work since it > + * generates a different encoding for additional KVM processing, and is > + * only suitable for userspace to access the register via ioctls. > + * Hence, define a 'pure' sys_reg() here to generate the encodings as per spec. > + */ > +#define sys_reg(op0, op1, crn, crm, op2) \ > + (((op0) << Op0_shift) | ((op1) << Op1_shift) | \ > + ((crn) << CRn_shift) | ((crm) << CRm_shift) | \ > + ((op2) << Op2_shift)) > + > +asm( > +" .irp num,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30\n" > +" .equ .L__reg_num_x\\num, \\num\n" > +" .endr\n" > +" .equ .L__reg_num_xzr, 31\n" > +"\n" > +" .macro mrs_s, rt, sreg\n" > +" .inst 0xd5200000|(\\sreg)|(.L__reg_num_\\rt)\n" > +" .endm\n" > +"\n" > +" .macro msr_s, sreg, rt\n" > +" .inst 0xd5000000|(\\sreg)|(.L__reg_num_\\rt)\n" > +" .endm\n" > +); > + > +/* > + * read_sysreg_s() and write_sysreg_s()'s 'reg' has to be encoded via sys_reg() > + */ > +#define read_sysreg_s(reg) ({ \ > + u64 __val; \ > + asm volatile("mrs_s %0, "__stringify(reg) : "=r" (__val)); \ > + __val; \ > +}) > + > +#define write_sysreg_s(reg, val) do { \ > + u64 __val = (u64)val; \ > + asm volatile("msr_s "__stringify(reg) ", %x0" : : "rZ" (__val));\ > +} while (0) > + > #define write_sysreg(reg, val) \ > ({ \ > u64 __val = (u64)(val); \ > -- > 2.33.0.153.gba50c8fa24-goog > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-23.3 required=3.0 tests=BAYES_00,DKIMWL_WL_MED, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS, USER_IN_DEF_DKIM_WL autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id C450AC432BE for ; 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[34.68.225.194]) by smtp.gmail.com with ESMTPSA id 7sm425362ilx.16.2021.09.01.14.28.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 Sep 2021 14:28:31 -0700 (PDT) Date: Wed, 1 Sep 2021 21:28:28 +0000 From: Oliver Upton To: Raghavendra Rao Ananta Cc: Paolo Bonzini , Marc Zyngier , James Morse , Alexandru Elisei , Suzuki K Poulose , Catalin Marinas , Will Deacon , Peter Shier , Ricardo Koller , Reiji Watanabe , Jing Zhang , linux-arm-kernel@lists.infradead.org, kvmarm@lists.cs.columbia.edu, linux-kernel@vger.kernel.org, kvm@vger.kernel.org Subject: Re: [PATCH v3 02/12] KVM: arm64: selftests: Add write_sysreg_s and read_sysreg_s Message-ID: References: <20210901211412.4171835-1-rananta@google.com> <20210901211412.4171835-3-rananta@google.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20210901211412.4171835-3-rananta@google.com> Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org On Wed, Sep 01, 2021 at 09:14:02PM +0000, Raghavendra Rao Ananta wrote: > For register names that are unsupported by the assembler or the ones > without architectural names, add the macros write_sysreg_s and > read_sysreg_s to support them. > > The functionality is derived from kvm-unit-tests and kernel's > arch/arm64/include/asm/sysreg.h. > > Signed-off-by: Raghavendra Rao Ananta Would it be possible to just include ? See tools/arch/arm64/include/asm/sysreg.h > --- > .../selftests/kvm/include/aarch64/processor.h | 61 +++++++++++++++++++ > 1 file changed, 61 insertions(+) > > diff --git a/tools/testing/selftests/kvm/include/aarch64/processor.h b/tools/testing/selftests/kvm/include/aarch64/processor.h > index 3cbaf5c1e26b..082cc97ad8d3 100644 > --- a/tools/testing/selftests/kvm/include/aarch64/processor.h > +++ b/tools/testing/selftests/kvm/include/aarch64/processor.h > @@ -118,6 +118,67 @@ void vm_install_exception_handler(struct kvm_vm *vm, > void vm_install_sync_handler(struct kvm_vm *vm, > int vector, int ec, handler_fn handler); > > +/* > + * ARMv8 ARM reserves the following encoding for system registers: > + * (Ref: ARMv8 ARM, Section: "System instruction class encoding overview", > + * C5.2, version:ARM DDI 0487A.f) > + * [20-19] : Op0 > + * [18-16] : Op1 > + * [15-12] : CRn > + * [11-8] : CRm > + * [7-5] : Op2 > + */ > +#define Op0_shift 19 > +#define Op0_mask 0x3 > +#define Op1_shift 16 > +#define Op1_mask 0x7 > +#define CRn_shift 12 > +#define CRn_mask 0xf > +#define CRm_shift 8 > +#define CRm_mask 0xf > +#define Op2_shift 5 > +#define Op2_mask 0x7 > + > +/* > + * When accessed from guests, the ARM64_SYS_REG() doesn't work since it > + * generates a different encoding for additional KVM processing, and is > + * only suitable for userspace to access the register via ioctls. > + * Hence, define a 'pure' sys_reg() here to generate the encodings as per spec. > + */ > +#define sys_reg(op0, op1, crn, crm, op2) \ > + (((op0) << Op0_shift) | ((op1) << Op1_shift) | \ > + ((crn) << CRn_shift) | ((crm) << CRm_shift) | \ > + ((op2) << Op2_shift)) > + > +asm( > +" .irp num,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30\n" > +" .equ .L__reg_num_x\\num, \\num\n" > +" .endr\n" > +" .equ .L__reg_num_xzr, 31\n" > +"\n" > +" .macro mrs_s, rt, sreg\n" > +" .inst 0xd5200000|(\\sreg)|(.L__reg_num_\\rt)\n" > +" .endm\n" > +"\n" > +" .macro msr_s, sreg, rt\n" > +" .inst 0xd5000000|(\\sreg)|(.L__reg_num_\\rt)\n" > +" .endm\n" > +); > + > +/* > + * read_sysreg_s() and write_sysreg_s()'s 'reg' has to be encoded via sys_reg() > + */ > +#define read_sysreg_s(reg) ({ \ > + u64 __val; \ > + asm volatile("mrs_s %0, "__stringify(reg) : "=r" (__val)); \ > + __val; \ > +}) > + > +#define write_sysreg_s(reg, val) do { \ > + u64 __val = (u64)val; \ > + asm volatile("msr_s "__stringify(reg) ", %x0" : : "rZ" (__val));\ > +} while (0) > + > #define write_sysreg(reg, val) \ > ({ \ > u64 __val = (u64)(val); \ > -- > 2.33.0.153.gba50c8fa24-goog >