From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-14.0 required=3.0 tests=BAYES_00,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8A1CBC432BE for ; Wed, 25 Aug 2021 15:45:58 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 6CA636054E for ; Wed, 25 Aug 2021 15:45:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240982AbhHYPqn (ORCPT ); Wed, 25 Aug 2021 11:46:43 -0400 Received: from mail-ot1-f46.google.com ([209.85.210.46]:37386 "EHLO mail-ot1-f46.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S240346AbhHYPqn (ORCPT ); Wed, 25 Aug 2021 11:46:43 -0400 Received: by mail-ot1-f46.google.com with SMTP id i3-20020a056830210300b0051af5666070so45701762otc.4; Wed, 25 Aug 2021 08:45:57 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:content-transfer-encoding :in-reply-to; bh=NsNMFFFFEFLAZuH245IhIJFqtd87059TgySDgcFY3v4=; b=EZSu7B9fxHSZthpjddds/j89ZCAfnEr4pFBSGgnMoV4TaMZvxyqH46NQroLdsRa33m QHzFp1GYsb3b1lp/T/HyIiAm7nY2eczCHc/ScR/hP0Xjr/6iEEc039wH0YaEggXMAewp T0tXpoftznOt0vADI0xuimLISBF6pJl6BChve6qgJQslQyP0sUzmPJKoZs25TihGAW4H PBvT6FYFHPMcVh/uHsxgHNp0LvGH6PtEBhfJ0YB/yNtg/FwqUN+p5FOanK8VXXGoUeyU dRhOf7oMPJLjPdqNVW995s2pInS/K29qhrD8yilxP39O/EVR7IzIjeJDtcN34LpNg454 HmOA== X-Gm-Message-State: AOAM532l0z+RGwbyGPbRd/Yb2m4rvi/zqway7/1V+xa2EH68nBvWbeMS pdA4obN5RHx54ff2FJaIfQ== X-Google-Smtp-Source: ABdhPJzfkJFZqWY/Z2lBCK5ZHgQG7fxjiA4+qlFfRwKE1NQPrJ7s0h5NwB9+cWUFrFbBdsAQHYl9nw== X-Received: by 2002:a05:6830:43a0:: with SMTP id s32mr13546006otv.284.1629906356700; Wed, 25 Aug 2021 08:45:56 -0700 (PDT) Received: from robh.at.kernel.org (66-90-148-213.dyn.grandenetworks.net. [66.90.148.213]) by smtp.gmail.com with ESMTPSA id w15sm41445oiw.19.2021.08.25.08.45.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Aug 2021 08:45:56 -0700 (PDT) Received: (nullmailer pid 2841976 invoked by uid 1000); Wed, 25 Aug 2021 15:45:54 -0000 Date: Wed, 25 Aug 2021 10:45:54 -0500 From: Rob Herring To: Baruch Siach Cc: Thierry Reding , Uwe =?iso-8859-1?Q?Kleine-K=F6nig?= , Lee Jones , Andy Gross , Bjorn Andersson , Balaji Prakash J , Robert Marko , Kathiravan T , linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: Re: [PATCH v7 3/4] dt-bindings: pwm: add IPQ6018 binding Message-ID: References: <3b70f9e757e018d3cd91a882282040c4c0589a93.1629884907.git.baruch@tkos.co.il> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org On Wed, Aug 25, 2021 at 12:48:26PM +0300, Baruch Siach wrote: > DT binding for the PWM block in Qualcomm IPQ6018 SoC. > > Signed-off-by: Baruch Siach > --- > v7: > > Use 'reg' instead of 'offset' (Rob) > > Drop 'clock-names' and 'assigned-clock*' (Bjorn) > > Use single cell address/size in example node (Bjorn) > > Move '#pwm-cells' lower in example node (Bjorn) > > List 'reg' as required > > v6: > > Device node is child of TCSR; remove phandle (Rob Herring) > > Add assigned-clocks/assigned-clock-rates (Uwe Kleine-König) > > v5: Use qcom,pwm-regs for phandle instead of direct regs (Bjorn > Andersson, Kathiravan T) > > v4: Update the binding example node as well (Rob Herring's bot) > > v3: s/qcom,pwm-ipq6018/qcom,ipq6018-pwm/ (Rob Herring) > > v2: Make #pwm-cells const (Rob Herring) > --- > .../devicetree/bindings/pwm/ipq-pwm.yaml | 52 +++++++++++++++++++ > 1 file changed, 52 insertions(+) > create mode 100644 Documentation/devicetree/bindings/pwm/ipq-pwm.yaml > > diff --git a/Documentation/devicetree/bindings/pwm/ipq-pwm.yaml b/Documentation/devicetree/bindings/pwm/ipq-pwm.yaml > new file mode 100644 > index 000000000000..edfec41e77e5 > --- /dev/null > +++ b/Documentation/devicetree/bindings/pwm/ipq-pwm.yaml > @@ -0,0 +1,52 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/pwm/ipq-pwm.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Qualcomm IPQ6018 PWM controller > + > +maintainers: > + - Baruch Siach > + > +properties: > + "#pwm-cells": > + const: 2 > + > + compatible: > + const: qcom,ipq6018-pwm > + > + reg: > + description: Offset of PWM register in the TCSR block. > + maxItems: 1 > + > + clocks: > + maxItems: 1 > + > +required: > + - compatible > + - reg > + - clocks > + - "#pwm-cells" > + > +additionalProperties: false > + > +examples: > + - | > + #include > + > + tcsr: syscon@1937000 { > + compatible = "qcom,tcsr-ipq6018", "syscon", "simple-mfd"; This needs to be documented. Some visibility into what else is in this block would be nice so we can make some informed decisions as to what all this should look like. > + reg = <0x01937000 0x21000>; > + #address-cells = <1>; > + #size-cells = <0>; > + > + pwm: pwm@a010 { > + compatible = "qcom,ipq6018-pwm"; > + reg = <0xa010>; There's not a length associated with the PWM registers. > + clocks = <&gcc GCC_ADSS_PWM_CLK>; > + assigned-clocks = <&gcc GCC_ADSS_PWM_CLK>; > + assigned-clock-rates = <100000000>; > + #pwm-cells = <2>; > + }; > + }; > -- > 2.32.0 > > From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-14.7 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A974FC4320A for ; Wed, 25 Aug 2021 15:48:00 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 75EFB610C7 for ; Wed, 25 Aug 2021 15:48:00 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 75EFB610C7 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=kernel.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:Cc:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=9av4gswyk/M2dUG+hrsjcD069AkXdjYxV3ctiZuhq+w=; b=hrEKxU8q0mqMc8 739MF7K+i1Ny+EYpPBqkmY8tMHTA9DcD7ouNlEB/PEHYzlf38Qnn0209bKslVnI0iQO32fApBypmA Btk3eEgx+whO+JSjov94V/v1Y1RV7VE2Cn+LcDu+5dTvleJxb/JwwHQRXRfVtoIdJTvDRNW+3gDr5 n4+J6U4GUKhkxc/ehWvAtqRnZjgCu136HQ5HIikMf+kmJoWg1Hwh9CmkmpG26xheLo6E0Br029v8b 5A+gvoXxNVe3OUY++6ShyJULqTt0NpDbOtEdYnwe39FF8jUBj42Llevqn/R4yillyiy4M+B+W5QUW bpe+wMGMswzhaxQXcRLA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1mIv6K-007b1R-1w; Wed, 25 Aug 2021 15:46:04 +0000 Received: from mail-ot1-f45.google.com ([209.85.210.45]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1mIv6E-007b0K-DT for linux-arm-kernel@lists.infradead.org; Wed, 25 Aug 2021 15:46:02 +0000 Received: by mail-ot1-f45.google.com with SMTP id a20-20020a0568300b9400b0051b8ca82dfcso34503561otv.3 for ; Wed, 25 Aug 2021 08:45:57 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:content-transfer-encoding :in-reply-to; bh=NsNMFFFFEFLAZuH245IhIJFqtd87059TgySDgcFY3v4=; b=I7WNZgboautcHSWHRiF6qKQBBWAe0G5+8C9ND6U2LwQ0rav1NWmiy3W0kwyL/M+SfG A4QCZoOK0sEnEVydlrqkhieftcqyAmNvlxMEB/L/SFa8P+TkZ7nrUHzzceOqHMo3VGVg wft5fOwEh15ajaolviSMRiVMCi/hMJpOpqoB5b/WiGXom5JPtzMojgNvjdEndWwLVb7a TrZIBjXlIC/LimWq9pnnJ7G5KAcsOD1yTTvRl3kLJguUd70O/OcsoHWYnRA61VmWMx1V pIJ0E3DMu1r2IwfiIzOXr9wfzVMO/IY0zXd63cRDXzcthPZa0J8X0x9QSC2YyeaWcW0+ XWnA== X-Gm-Message-State: AOAM533CpdsXGBNsm1eJ5dO/IshLcOYUH3vHbH0V415MjP/we1tm4KNA H6tbptwPeBXptNuFU2heZlpdpqLuVA== X-Google-Smtp-Source: ABdhPJzfkJFZqWY/Z2lBCK5ZHgQG7fxjiA4+qlFfRwKE1NQPrJ7s0h5NwB9+cWUFrFbBdsAQHYl9nw== X-Received: by 2002:a05:6830:43a0:: with SMTP id s32mr13546006otv.284.1629906356700; Wed, 25 Aug 2021 08:45:56 -0700 (PDT) Received: from robh.at.kernel.org (66-90-148-213.dyn.grandenetworks.net. [66.90.148.213]) by smtp.gmail.com with ESMTPSA id w15sm41445oiw.19.2021.08.25.08.45.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Aug 2021 08:45:56 -0700 (PDT) Received: (nullmailer pid 2841976 invoked by uid 1000); Wed, 25 Aug 2021 15:45:54 -0000 Date: Wed, 25 Aug 2021 10:45:54 -0500 From: Rob Herring To: Baruch Siach Cc: Thierry Reding , Uwe =?iso-8859-1?Q?Kleine-K=F6nig?= , Lee Jones , Andy Gross , Bjorn Andersson , Balaji Prakash J , Robert Marko , Kathiravan T , linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: Re: [PATCH v7 3/4] dt-bindings: pwm: add IPQ6018 binding Message-ID: References: <3b70f9e757e018d3cd91a882282040c4c0589a93.1629884907.git.baruch@tkos.co.il> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210825_084558_509701_F0AA054D X-CRM114-Status: GOOD ( 21.43 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Wed, Aug 25, 2021 at 12:48:26PM +0300, Baruch Siach wrote: > DT binding for the PWM block in Qualcomm IPQ6018 SoC. > = > Signed-off-by: Baruch Siach > --- > v7: > = > Use 'reg' instead of 'offset' (Rob) > = > Drop 'clock-names' and 'assigned-clock*' (Bjorn) > = > Use single cell address/size in example node (Bjorn) > = > Move '#pwm-cells' lower in example node (Bjorn) > = > List 'reg' as required > = > v6: > = > Device node is child of TCSR; remove phandle (Rob Herring) > = > Add assigned-clocks/assigned-clock-rates (Uwe Kleine-K=F6nig) > = > v5: Use qcom,pwm-regs for phandle instead of direct regs (Bjorn > Andersson, Kathiravan T) > = > v4: Update the binding example node as well (Rob Herring's bot) > = > v3: s/qcom,pwm-ipq6018/qcom,ipq6018-pwm/ (Rob Herring) > = > v2: Make #pwm-cells const (Rob Herring) > --- > .../devicetree/bindings/pwm/ipq-pwm.yaml | 52 +++++++++++++++++++ > 1 file changed, 52 insertions(+) > create mode 100644 Documentation/devicetree/bindings/pwm/ipq-pwm.yaml > = > diff --git a/Documentation/devicetree/bindings/pwm/ipq-pwm.yaml b/Documen= tation/devicetree/bindings/pwm/ipq-pwm.yaml > new file mode 100644 > index 000000000000..edfec41e77e5 > --- /dev/null > +++ b/Documentation/devicetree/bindings/pwm/ipq-pwm.yaml > @@ -0,0 +1,52 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/pwm/ipq-pwm.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Qualcomm IPQ6018 PWM controller > + > +maintainers: > + - Baruch Siach > + > +properties: > + "#pwm-cells": > + const: 2 > + > + compatible: > + const: qcom,ipq6018-pwm > + > + reg: > + description: Offset of PWM register in the TCSR block. > + maxItems: 1 > + > + clocks: > + maxItems: 1 > + > +required: > + - compatible > + - reg > + - clocks > + - "#pwm-cells" > + > +additionalProperties: false > + > +examples: > + - | > + #include > + > + tcsr: syscon@1937000 { > + compatible =3D "qcom,tcsr-ipq6018", "syscon", "simple-mfd"; This needs to be documented. Some visibility into what else is in this = block would be nice so we can make some informed decisions as to what = all this should look like. > + reg =3D <0x01937000 0x21000>; > + #address-cells =3D <1>; > + #size-cells =3D <0>; > + > + pwm: pwm@a010 { > + compatible =3D "qcom,ipq6018-pwm"; > + reg =3D <0xa010>; There's not a length associated with the PWM registers. > + clocks =3D <&gcc GCC_ADSS_PWM_CLK>; > + assigned-clocks =3D <&gcc GCC_ADSS_PWM_CLK>; > + assigned-clock-rates =3D <100000000>; > + #pwm-cells =3D <2>; > + }; > + }; > -- = > 2.32.0 > = > = _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel