Re: [PATCH v3 7/9] clk: imx: Update the pfdv2 for 8ulp specific support

[Abel Vesa <abel.vesa@nxp.com>]

On 21-09-14 14:52:06, Jacky Bai wrote:
> On i.MX8ULP, the 'CLK_SET_RATE_PARENT' flag should NOT be
> set and according to the laest RM, the PFD divider value range
> seems will be changed in the future, so update the pfdv2 to
> include the specific support for i.MX8ULP.
> 
> Signed-off-by: Jacky Bai <ping.bai@nxp.com>

Reviewed-by: Abel Vesa <abel.vesa@nxp.com>

> ---
>   v3 changs: no
> ---
>  drivers/clk/imx/clk-imx7ulp.c | 16 ++++++++--------
>  drivers/clk/imx/clk-pfdv2.c   |  9 ++++++---
>  drivers/clk/imx/clk.h         |  9 +++++++--
>  3 files changed, 21 insertions(+), 13 deletions(-)
> 
> diff --git a/drivers/clk/imx/clk-imx7ulp.c b/drivers/clk/imx/clk-imx7ulp.c
> index ba50d6db8097..b6e45e77ee39 100644
> --- a/drivers/clk/imx/clk-imx7ulp.c
> +++ b/drivers/clk/imx/clk-imx7ulp.c
> @@ -82,16 +82,16 @@ static void __init imx7ulp_clk_scg1_init(struct device_node *np)
>  	hws[IMX7ULP_CLK_SPLL]		= imx_clk_hw_pllv4(IMX_PLLV4_IMX7ULP, "spll",  "spll_pre_div", base + 0x600);
>  
>  	/* APLL PFDs */
> -	hws[IMX7ULP_CLK_APLL_PFD0]	= imx_clk_hw_pfdv2("apll_pfd0", "apll", base + 0x50c, 0);
> -	hws[IMX7ULP_CLK_APLL_PFD1]	= imx_clk_hw_pfdv2("apll_pfd1", "apll", base + 0x50c, 1);
> -	hws[IMX7ULP_CLK_APLL_PFD2]	= imx_clk_hw_pfdv2("apll_pfd2", "apll", base + 0x50c, 2);
> -	hws[IMX7ULP_CLK_APLL_PFD3]	= imx_clk_hw_pfdv2("apll_pfd3", "apll", base + 0x50c, 3);
> +	hws[IMX7ULP_CLK_APLL_PFD0]	= imx_clk_hw_pfdv2(IMX_PFDV2_IMX7ULP, "apll_pfd0", "apll", base + 0x50c, 0);
> +	hws[IMX7ULP_CLK_APLL_PFD1]	= imx_clk_hw_pfdv2(IMX_PFDV2_IMX7ULP, "apll_pfd1", "apll", base + 0x50c, 1);
> +	hws[IMX7ULP_CLK_APLL_PFD2]	= imx_clk_hw_pfdv2(IMX_PFDV2_IMX7ULP, "apll_pfd2", "apll", base + 0x50c, 2);
> +	hws[IMX7ULP_CLK_APLL_PFD3]	= imx_clk_hw_pfdv2(IMX_PFDV2_IMX7ULP, "apll_pfd3", "apll", base + 0x50c, 3);
>  
>  	/* SPLL PFDs */
> -	hws[IMX7ULP_CLK_SPLL_PFD0]	= imx_clk_hw_pfdv2("spll_pfd0", "spll", base + 0x60C, 0);
> -	hws[IMX7ULP_CLK_SPLL_PFD1]	= imx_clk_hw_pfdv2("spll_pfd1", "spll", base + 0x60C, 1);
> -	hws[IMX7ULP_CLK_SPLL_PFD2]	= imx_clk_hw_pfdv2("spll_pfd2", "spll", base + 0x60C, 2);
> -	hws[IMX7ULP_CLK_SPLL_PFD3]	= imx_clk_hw_pfdv2("spll_pfd3", "spll", base + 0x60C, 3);
> +	hws[IMX7ULP_CLK_SPLL_PFD0]	= imx_clk_hw_pfdv2(IMX_PFDV2_IMX7ULP, "spll_pfd0", "spll", base + 0x60C, 0);
> +	hws[IMX7ULP_CLK_SPLL_PFD1]	= imx_clk_hw_pfdv2(IMX_PFDV2_IMX7ULP, "spll_pfd1", "spll", base + 0x60C, 1);
> +	hws[IMX7ULP_CLK_SPLL_PFD2]	= imx_clk_hw_pfdv2(IMX_PFDV2_IMX7ULP, "spll_pfd2", "spll", base + 0x60C, 2);
> +	hws[IMX7ULP_CLK_SPLL_PFD3]	= imx_clk_hw_pfdv2(IMX_PFDV2_IMX7ULP, "spll_pfd3", "spll", base + 0x60C, 3);
>  
>  	/* PLL Mux */
>  	hws[IMX7ULP_CLK_APLL_PFD_SEL]	= imx_clk_hw_mux_flags("apll_pfd_sel", base + 0x508, 14, 2, apll_pfd_sels, ARRAY_SIZE(apll_pfd_sels), CLK_SET_RATE_PARENT | CLK_SET_PARENT_GATE);
> diff --git a/drivers/clk/imx/clk-pfdv2.c b/drivers/clk/imx/clk-pfdv2.c
> index 9cba83521988..42505669cdfb 100644
> --- a/drivers/clk/imx/clk-pfdv2.c
> +++ b/drivers/clk/imx/clk-pfdv2.c
> @@ -200,8 +200,8 @@ static const struct clk_ops clk_pfdv2_ops = {
>  	.is_enabled     = clk_pfdv2_is_enabled,
>  };
>  
> -struct clk_hw *imx_clk_hw_pfdv2(const char *name, const char *parent_name,
> -			     void __iomem *reg, u8 idx)
> +struct clk_hw *imx_clk_hw_pfdv2(enum imx_pfdv2_type type, const char *name,
> +			     const char *parent_name, void __iomem *reg, u8 idx)
>  {
>  	struct clk_init_data init;
>  	struct clk_pfdv2 *pfd;
> @@ -223,7 +223,10 @@ struct clk_hw *imx_clk_hw_pfdv2(const char *name, const char *parent_name,
>  	init.ops = &clk_pfdv2_ops;
>  	init.parent_names = &parent_name;
>  	init.num_parents = 1;
> -	init.flags = CLK_SET_RATE_GATE | CLK_SET_RATE_PARENT;
> +	if (type == IMX_PFDV2_IMX7ULP)
> +		init.flags = CLK_SET_RATE_GATE | CLK_SET_RATE_PARENT;
> +	else
> +		init.flags = CLK_SET_RATE_GATE;
>  
>  	pfd->hw.init = &init;
>  
> diff --git a/drivers/clk/imx/clk.h b/drivers/clk/imx/clk.h
> index a9bcfee7a75b..45be7ba23fae 100644
> --- a/drivers/clk/imx/clk.h
> +++ b/drivers/clk/imx/clk.h
> @@ -47,6 +47,11 @@ enum imx_pllv4_type {
>  	IMX_PLLV4_IMX8ULP,
>  };
>  
> +enum imx_pfdv2_type {
> +	IMX_PFDV2_IMX7ULP,
> +	IMX_PFDV2_IMX8ULP,
> +};
> +
>  /* NOTE: Rate table should be kept sorted in descending order. */
>  struct imx_pll14xx_rate_table {
>  	unsigned int rate;
> @@ -220,8 +225,8 @@ struct clk_hw *imx_clk_hw_gate_exclusive(const char *name, const char *parent,
>  struct clk_hw *imx_clk_hw_pfd(const char *name, const char *parent_name,
>  		void __iomem *reg, u8 idx);
>  
> -struct clk_hw *imx_clk_hw_pfdv2(const char *name, const char *parent_name,
> -			     void __iomem *reg, u8 idx);
> +struct clk_hw *imx_clk_hw_pfdv2(enum imx_pfdv2_type type, const char *name,
> +	 const char *parent_name, void __iomem *reg, u8 idx);
>  
>  struct clk_hw *imx_clk_hw_busy_divider(const char *name, const char *parent_name,
>  				 void __iomem *reg, u8 shift, u8 width,
> -- 
> 2.26.2
>