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(version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 29 Sep 2021 06:28:07 -0700 (PDT) Date: Wed, 29 Sep 2021 09:28:06 -0400 From: Darius Rad To: Greentime Hu Cc: linux-riscv , Linux Kernel Mailing List , Albert Ou , Palmer Dabbelt , Paul Walmsley , Vincent Chen Subject: Re: [RFC PATCH v8 09/21] riscv: Add task switch support for vector Message-ID: References: <0e65c165e3d54a38cbba01603f325dca727274de.1631121222.git.greentime.hu@sifive.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210929_062810_599609_2F8F40CE X-CRM114-Status: GOOD ( 50.74 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org T24gVHVlLCBTZXAgMjgsIDIwMjEgYXQgMTA6NTY6NTJQTSArMDgwMCwgR3JlZW50aW1lIEh1IHdy b3RlOgo+IERhcml1cyBSYWQgPGRhcml1c0BibHVlc3BlYy5jb20+IOaWvCAyMDIx5bm0OeaciDEz 5pelIOmAseS4gCDkuIvljYg4OjIx5a+r6YGT77yaCj4gPgo+ID4gT24gOS84LzIxIDE6NDUgUE0s IEdyZWVudGltZSBIdSB3cm90ZToKPiA+ID4gVGhpcyBwYXRjaCBhZGRzIHRhc2sgc3dpdGNoIHN1 cHBvcnQgZm9yIHZlY3Rvci4gSXQgc3VwcG9ydHMgcGFydGlhbCBsYXp5Cj4gPiA+IHNhdmUgYW5k IHJlc3RvcmUgbWVjaGFuaXNtLiBJdCBhbHNvIHN1cHBvcnRzIGFsbCBsZW5ndGhzIG9mIHZsZW4u Cj4gPiA+Cj4gPiA+IFtndW9yZW5AbGludXguYWxpYmFiYS5jb206IEZpcnN0IGF2YWlsYWJsZSBw b3J0aW5nIHRvIHN1cHBvcnQgdmVjdG9yCj4gPiA+IGNvbnRleHQgc3dpdGNoaW5nXQo+ID4gPiBb bmljay5rbmlnaHRAc2lmaXZlLmNvbTogUmV3cml0ZSB2ZWN0b3IuUyB0byBzdXBwb3J0IGR5bmFt aWMgdmxlbiwgeGxlbiBhbmQKPiA+ID4gY29kZSByZWZpbmVdCj4gPiA+IFt2aW5jZW50LmNoZW5A c2lmaXZlLmNvOiBGaXggdGhlIG1pZ2h0X3NsZWVwIGlzc3VlIGluIHZzdGF0ZV9zYXZlLAo+ID4g PiB2c3RhdGVfcmVzdG9yZV0KPiA+ID4gQ28tZGV2ZWxvcGVkLWJ5OiBOaWNrIEtuaWdodCA8bmlj ay5rbmlnaHRAc2lmaXZlLmNvbT4KPiA+ID4gU2lnbmVkLW9mZi1ieTogTmljayBLbmlnaHQgPG5p Y2sua25pZ2h0QHNpZml2ZS5jb20+Cj4gPiA+IENvLWRldmVsb3BlZC1ieTogR3VvIFJlbiA8Z3Vv cmVuQGxpbnV4LmFsaWJhYmEuY29tPgo+ID4gPiBTaWduZWQtb2ZmLWJ5OiBHdW8gUmVuIDxndW9y ZW5AbGludXguYWxpYmFiYS5jb20+Cj4gPiA+IENvLWRldmVsb3BlZC1ieTogVmluY2VudCBDaGVu IDx2aW5jZW50LmNoZW5Ac2lmaXZlLmNvbT4KPiA+ID4gU2lnbmVkLW9mZi1ieTogVmluY2VudCBD aGVuIDx2aW5jZW50LmNoZW5Ac2lmaXZlLmNvbT4KPiA+ID4gU2lnbmVkLW9mZi1ieTogR3JlZW50 aW1lIEh1IDxncmVlbnRpbWUuaHVAc2lmaXZlLmNvbT4KPiA+ID4gLS0tCj4gPiA+ICAgYXJjaC9y aXNjdi9pbmNsdWRlL2FzbS9zd2l0Y2hfdG8uaCB8IDY2ICsrKysrKysrKysrKysrKysrKysrKysr Cj4gPiA+ICAgYXJjaC9yaXNjdi9rZXJuZWwvTWFrZWZpbGUgICAgICAgICB8ICAxICsKPiA+ID4g ICBhcmNoL3Jpc2N2L2tlcm5lbC9wcm9jZXNzLmMgICAgICAgIHwgMzggKysrKysrKysrKysrKysK PiA+ID4gICBhcmNoL3Jpc2N2L2tlcm5lbC92ZWN0b3IuUyAgICAgICAgIHwgODQgKysrKysrKysr KysrKysrKysrKysrKysrKysrKysrCj4gPiA+ICAgNCBmaWxlcyBjaGFuZ2VkLCAxODkgaW5zZXJ0 aW9ucygrKQo+ID4gPiAgIGNyZWF0ZSBtb2RlIDEwMDY0NCBhcmNoL3Jpc2N2L2tlcm5lbC92ZWN0 b3IuUwo+ID4gPgo+ID4gPiBkaWZmIC0tZ2l0IGEvYXJjaC9yaXNjdi9pbmNsdWRlL2FzbS9zd2l0 Y2hfdG8uaCBiL2FyY2gvcmlzY3YvaW5jbHVkZS9hc20vc3dpdGNoX3RvLmgKPiA+ID4gaW5kZXgg ZWM4Mzc3MGIzZDk4Li5kZTA1NzNkYWQ3OGYgMTAwNjQ0Cj4gPiA+IC0tLSBhL2FyY2gvcmlzY3Yv aW5jbHVkZS9hc20vc3dpdGNoX3RvLmgKPiA+ID4gKysrIGIvYXJjaC9yaXNjdi9pbmNsdWRlL2Fz bS9zd2l0Y2hfdG8uaAo+ID4gPiBAQCAtNywxMCArNywxMiBAQAo+ID4gPiAgICNkZWZpbmUgX0FT TV9SSVNDVl9TV0lUQ0hfVE9fSAo+ID4gPgo+ID4gPiAgICNpbmNsdWRlIDxsaW51eC9qdW1wX2xh YmVsLmg+Cj4gPiA+ICsjaW5jbHVkZSA8bGludXgvc2xhYi5oPgo+ID4gPiAgICNpbmNsdWRlIDxs aW51eC9zY2hlZC90YXNrX3N0YWNrLmg+Cj4gPiA+ICAgI2luY2x1ZGUgPGFzbS9wcm9jZXNzb3Iu aD4KPiA+ID4gICAjaW5jbHVkZSA8YXNtL3B0cmFjZS5oPgo+ID4gPiAgICNpbmNsdWRlIDxhc20v Y3NyLmg+Cj4gPiA+ICsjaW5jbHVkZSA8YXNtL2FzbS1vZmZzZXRzLmg+Cj4gPiA+Cj4gPiA+ICAg I2lmZGVmIENPTkZJR19GUFUKPiA+ID4gICBleHRlcm4gdm9pZCBfX2ZzdGF0ZV9zYXZlKHN0cnVj dCB0YXNrX3N0cnVjdCAqc2F2ZV90byk7Cj4gPiA+IEBAIC02OCw2ICs3MCw2OCBAQCBzdGF0aWMg X19hbHdheXNfaW5saW5lIGJvb2wgaGFzX2ZwdSh2b2lkKSB7IHJldHVybiBmYWxzZTsgfQo+ID4g PiAgICNkZWZpbmUgX19zd2l0Y2hfdG9fZnB1KF9fcHJldiwgX19uZXh0KSBkbyB7IH0gd2hpbGUg KDApCj4gPiA+ICAgI2VuZGlmCj4gPiA+Cj4gPiA+ICsjaWZkZWYgQ09ORklHX1ZFQ1RPUgo+ID4g PiArZXh0ZXJuIGJvb2wgaGFzX3ZlY3RvcjsKPiA+ID4gK2V4dGVybiB1bnNpZ25lZCBsb25nIHJp c2N2X3ZzaXplOwo+ID4gPiArZXh0ZXJuIHZvaWQgX192c3RhdGVfc2F2ZShzdHJ1Y3QgX19yaXNj dl92X3N0YXRlICpzYXZlX3RvLCB2b2lkICpkYXRhcCk7Cj4gPiA+ICtleHRlcm4gdm9pZCBfX3Zz dGF0ZV9yZXN0b3JlKHN0cnVjdCBfX3Jpc2N2X3Zfc3RhdGUgKnJlc3RvcmVfZnJvbSwgdm9pZCAq ZGF0YXApOwo+ID4gPiArCj4gPiA+ICtzdGF0aWMgaW5saW5lIHZvaWQgX192c3RhdGVfY2xlYW4o c3RydWN0IHB0X3JlZ3MgKnJlZ3MpCj4gPiA+ICt7Cj4gPiA+ICsgICAgIHJlZ3MtPnN0YXR1cyA9 IChyZWdzLT5zdGF0dXMgJiB+KFNSX1ZTKSkgfCBTUl9WU19DTEVBTjsKPiA+ID4gK30KPiA+ID4g Kwo+ID4gPiArc3RhdGljIGlubGluZSB2b2lkIHZzdGF0ZV9vZmYoc3RydWN0IHRhc2tfc3RydWN0 ICp0YXNrLAo+ID4gPiArICAgICAgICAgICAgICAgICAgICAgICAgICAgc3RydWN0IHB0X3JlZ3Mg KnJlZ3MpCj4gPiA+ICt7Cj4gPiA+ICsgICAgIHJlZ3MtPnN0YXR1cyA9IChyZWdzLT5zdGF0dXMg JiB+U1JfVlMpIHwgU1JfVlNfT0ZGOwo+ID4gPiArfQo+ID4gPiArCj4gPiA+ICtzdGF0aWMgaW5s aW5lIHZvaWQgdnN0YXRlX3NhdmUoc3RydWN0IHRhc2tfc3RydWN0ICp0YXNrLAo+ID4gPiArICAg ICAgICAgICAgICAgICAgICAgICAgICAgIHN0cnVjdCBwdF9yZWdzICpyZWdzKQo+ID4gPiArewo+ ID4gPiArICAgICBpZiAoKHJlZ3MtPnN0YXR1cyAmIFNSX1ZTKSA9PSBTUl9WU19ESVJUWSkgewo+ ID4gPiArICAgICAgICAgICAgIHN0cnVjdCBfX3Jpc2N2X3Zfc3RhdGUgKnZzdGF0ZSA9ICYodGFz ay0+dGhyZWFkLnZzdGF0ZSk7Cj4gPiA+ICsKPiA+ID4gKyAgICAgICAgICAgICBfX3ZzdGF0ZV9z YXZlKHZzdGF0ZSwgdnN0YXRlLT5kYXRhcCk7Cj4gPiA+ICsgICAgICAgICAgICAgX192c3RhdGVf Y2xlYW4ocmVncyk7Cj4gPiA+ICsgICAgIH0KPiA+ID4gK30KPiA+ID4gKwo+ID4gPiArc3RhdGlj IGlubGluZSB2b2lkIHZzdGF0ZV9yZXN0b3JlKHN0cnVjdCB0YXNrX3N0cnVjdCAqdGFzaywKPiA+ ID4gKyAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICBzdHJ1Y3QgcHRfcmVncyAqcmVncykK PiA+ID4gK3sKPiA+ID4gKyAgICAgaWYgKChyZWdzLT5zdGF0dXMgJiBTUl9WUykgIT0gU1JfVlNf T0ZGKSB7Cj4gPiA+ICsgICAgICAgICAgICAgc3RydWN0IF9fcmlzY3Zfdl9zdGF0ZSAqdnN0YXRl ID0gJih0YXNrLT50aHJlYWQudnN0YXRlKTsKPiA+ID4gKwo+ID4gPiArICAgICAgICAgICAgIC8q IEFsbG9jYXRlIHNwYWNlIGZvciB2ZWN0b3IgcmVnaXN0ZXJzLiAqLwo+ID4gPiArICAgICAgICAg ICAgIGlmICghdnN0YXRlLT5kYXRhcCkgewo+ID4gPiArICAgICAgICAgICAgICAgICAgICAgdnN0 YXRlLT5kYXRhcCA9IGt6YWxsb2MocmlzY3ZfdnNpemUsIEdGUF9BVE9NSUMpOwo+ID4gPiArICAg ICAgICAgICAgICAgICAgICAgdnN0YXRlLT5zaXplID0gcmlzY3ZfdnNpemU7Cj4gPiA+ICsgICAg ICAgICAgICAgfQo+ID4gPiArICAgICAgICAgICAgIF9fdnN0YXRlX3Jlc3RvcmUodnN0YXRlLCB2 c3RhdGUtPmRhdGFwKTsKPiA+ID4gKyAgICAgICAgICAgICBfX3ZzdGF0ZV9jbGVhbihyZWdzKTsK PiA+ID4gKyAgICAgfQo+ID4gPiArfQo+ID4gPiArCj4gPiA+ICtzdGF0aWMgaW5saW5lIHZvaWQg X19zd2l0Y2hfdG9fdmVjdG9yKHN0cnVjdCB0YXNrX3N0cnVjdCAqcHJldiwKPiA+ID4gKyAgICAg ICAgICAgICAgICAgICAgICAgICAgICAgICAgc3RydWN0IHRhc2tfc3RydWN0ICpuZXh0KQo+ID4g PiArewo+ID4gPiArICAgICBzdHJ1Y3QgcHRfcmVncyAqcmVnczsKPiA+ID4gKwo+ID4gPiArICAg ICByZWdzID0gdGFza19wdF9yZWdzKHByZXYpOwo+ID4gPiArICAgICBpZiAodW5saWtlbHkocmVn cy0+c3RhdHVzICYgU1JfU0QpKQo+ID4gPiArICAgICAgICAgICAgIHZzdGF0ZV9zYXZlKHByZXYs IHJlZ3MpOwo+ID4gPiArICAgICB2c3RhdGVfcmVzdG9yZShuZXh0LCB0YXNrX3B0X3JlZ3MobmV4 dCkpOwo+ID4gPiArfQo+ID4gPiArCj4gPiA+ICsjZWxzZQo+ID4gPiArI2RlZmluZSBoYXNfdmVj dG9yIGZhbHNlCj4gPiA+ICsjZGVmaW5lIHZzdGF0ZV9zYXZlKHRhc2ssIHJlZ3MpIGRvIHsgfSB3 aGlsZSAoMCkKPiA+ID4gKyNkZWZpbmUgdnN0YXRlX3Jlc3RvcmUodGFzaywgcmVncykgZG8geyB9 IHdoaWxlICgwKQo+ID4gPiArI2RlZmluZSBfX3N3aXRjaF90b192ZWN0b3IoX19wcmV2LCBfX25l eHQpIGRvIHsgfSB3aGlsZSAoMCkKPiA+ID4gKyNlbmRpZgo+ID4gPiArCj4gPiA+ICAgZXh0ZXJu IHN0cnVjdCB0YXNrX3N0cnVjdCAqX19zd2l0Y2hfdG8oc3RydWN0IHRhc2tfc3RydWN0ICosCj4g PiA+ICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICBzdHJ1Y3QgdGFza19zdHJ1 Y3QgKik7Cj4gPiA+Cj4gPiA+IEBAIC03Nyw2ICsxNDEsOCBAQCBkbyB7ICAgICAgICAgICAgICAg ICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgIFwKPiA+ID4gICAgICAgc3Ry dWN0IHRhc2tfc3RydWN0ICpfX25leHQgPSAobmV4dCk7ICAgICAgICAgICAgXAo+ID4gPiAgICAg ICBpZiAoaGFzX2ZwdSgpKSAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICBcCj4gPiA+ ICAgICAgICAgICAgICAgX19zd2l0Y2hfdG9fZnB1KF9fcHJldiwgX19uZXh0KTsgICAgICAgIFwK PiA+ID4gKyAgICAgaWYgKGhhc192ZWN0b3IpICAgICAgICAgICAgICAgICAgICAgICAgICAgICAg ICAgXAo+ID4gPiArICAgICAgICAgICAgIF9fc3dpdGNoX3RvX3ZlY3RvcihfX3ByZXYsIF9fbmV4 dCk7ICAgICBcCj4gPiA+ICAgICAgICgobGFzdCkgPSBfX3N3aXRjaF90byhfX3ByZXYsIF9fbmV4 dCkpOyAgICAgICAgIFwKPiA+ID4gICB9IHdoaWxlICgwKQo+ID4gPgo+ID4gPiBkaWZmIC0tZ2l0 IGEvYXJjaC9yaXNjdi9rZXJuZWwvTWFrZWZpbGUgYi9hcmNoL3Jpc2N2L2tlcm5lbC9NYWtlZmls ZQo+ID4gPiBpbmRleCAzMzk3ZGRhYzFhMzAuLjM0NDA3ODA4MDgzOSAxMDA2NDQKPiA+ID4gLS0t IGEvYXJjaC9yaXNjdi9rZXJuZWwvTWFrZWZpbGUKPiA+ID4gKysrIGIvYXJjaC9yaXNjdi9rZXJu ZWwvTWFrZWZpbGUKPiA+ID4gQEAgLTQwLDYgKzQwLDcgQEAgb2JqLSQoQ09ORklHX01NVSkgKz0g dmRzby5vIHZkc28vCj4gPiA+Cj4gPiA+ICAgb2JqLSQoQ09ORklHX1JJU0NWX01fTU9ERSkgICs9 IHRyYXBzX21pc2FsaWduZWQubwo+ID4gPiAgIG9iai0kKENPTkZJR19GUFUpICAgICAgICAgICAr PSBmcHUubwo+ID4gPiArb2JqLSQoQ09ORklHX1ZFQ1RPUikgICAgICAgICArPSB2ZWN0b3Iubwo+ ID4gPiAgIG9iai0kKENPTkZJR19TTVApICAgICAgICAgICArPSBzbXBib290Lm8KPiA+ID4gICBv YmotJChDT05GSUdfU01QKSAgICAgICAgICAgKz0gc21wLm8KPiA+ID4gICBvYmotJChDT05GSUdf U01QKSAgICAgICAgICAgKz0gY3B1X29wcy5vCj4gPiA+IGRpZmYgLS1naXQgYS9hcmNoL3Jpc2N2 L2tlcm5lbC9wcm9jZXNzLmMgYi9hcmNoL3Jpc2N2L2tlcm5lbC9wcm9jZXNzLmMKPiA+ID4gaW5k ZXggMDNhYzNhYTYxMWY1Li4wYjg2ZTllNTMxYzkgMTAwNjQ0Cj4gPiA+IC0tLSBhL2FyY2gvcmlz Y3Yva2VybmVsL3Byb2Nlc3MuYwo+ID4gPiArKysgYi9hcmNoL3Jpc2N2L2tlcm5lbC9wcm9jZXNz LmMKPiA+ID4gQEAgLTk1LDYgKzk1LDE2IEBAIHZvaWQgc3RhcnRfdGhyZWFkKHN0cnVjdCBwdF9y ZWdzICpyZWdzLCB1bnNpZ25lZCBsb25nIHBjLAo+ID4gPiAgICAgICAgICAgICAgICAqLwo+ID4g PiAgICAgICAgICAgICAgIGZzdGF0ZV9yZXN0b3JlKGN1cnJlbnQsIHJlZ3MpOwo+ID4gPiAgICAg ICB9Cj4gPiA+ICsKPiA+ID4gKyAgICAgaWYgKGhhc192ZWN0b3IpIHsKPiA+ID4gKyAgICAgICAg ICAgICByZWdzLT5zdGF0dXMgfD0gU1JfVlNfSU5JVElBTDsKPiA+ID4gKyAgICAgICAgICAgICAv Kgo+ID4gPiArICAgICAgICAgICAgICAqIFJlc3RvcmUgdGhlIGluaXRpYWwgdmFsdWUgdG8gdGhl IHZlY3RvciByZWdpc3Rlcgo+ID4gPiArICAgICAgICAgICAgICAqIGJlZm9yZSBzdGFydGluZyB0 aGUgdXNlciBwcm9ncmFtLgo+ID4gPiArICAgICAgICAgICAgICAqLwo+ID4gPiArICAgICAgICAg ICAgIHZzdGF0ZV9yZXN0b3JlKGN1cnJlbnQsIHJlZ3MpOwo+ID4gPiArICAgICB9Cj4gPiA+ICsK PiA+Cj4gPiBTbyB0aGlzIHdpbGwgdW5jb25kaXRpb25hbGx5IGVuYWJsZSB2ZWN0b3IgaW5zdHJ1 Y3Rpb25zLCBhbmQgYWxsb2NhdGUKPiA+IG1lbW9yeSBmb3IgdmVjdG9yIHN0YXRlLCBmb3IgYWxs IHByb2Nlc3NlcywgcmVnYXJkbGVzcyBvZiB3aGV0aGVyIHZlY3Rvcgo+ID4gaW5zdHJ1Y3Rpb25z IGFyZSB1c2VkPwo+ID4KPiAKPiBIaSBEYXJpdXMsCj4gCj4gWWVzLCBpdCB3aWxsIGVuYWJsZSB2 ZWN0b3IgaWYgaGFzX3ZlY3RvcigpIGlzIHRydWUuIFRoZSByZWFzb24gdGhhdCB3ZQo+IGNob29z ZSB0byBlbmFibGUgYW5kIGFsbG9jYXRlIG1lbW9yeSBmb3IgdXNlciBzcGFjZSBwcm9ncmFtIGlz IGJlY2F1c2UKPiB3ZSBhbHNvIGltcGxlbWVudCBzb21lIGNvbW1vbiBmdW5jdGlvbnMgaW4gdGhl IGdsaWJjIHN1Y2ggYXMgbWVtY3B5Cj4gdmVjdG9yIHZlcnNpb24gYW5kIGl0IGlzIGNhbGxlZCB2 ZXJ5IG9mdGVuIGJ5IGV2ZXJ5IHByb2Nlc3MuIFNvIHRoYXQKPiB3ZSBhc3N1bWUgaWYgdGhlIHVz ZXIgcHJvZ3JhbSBpcyBydW5uaW5nIGluIGEgQ1BVIHdpdGggdmVjdG9yIElTQQo+IHdvdWxkIGxp a2UgdG8gdXNlIHZlY3RvciBieSBkZWZhdWx0LiBJZiB3ZSBkaXNhYmxlIGl0IGJ5IGRlZmF1bHQg YW5kCj4gbWFrZSBpdCB0cmlnZ2VyIHRoZSBpbGxlZ2FsIGluc3RydWN0aW9uLCB0aGF0IG1pZ2h0 IGJlIGEgYnVyZGVuIHNpbmNlCj4gYWxtb3N0IGV2ZXJ5IHByb2Nlc3Mgd2lsbCB1c2UgdmVjdG9y IGdsaWJjIG1lbWNweSBvciBzb21ldGhpbmcgbGlrZQo+IHRoYXQuCgpEbyB5b3UgaGF2ZSBhbnkg ZXZpZGVuY2UgdG8gc3VwcG9ydCB0aGUgYXNzZXJ0aW9uIHRoYXQgYWxtb3N0IGV2ZXJ5IHByb2Nl c3MKd291bGQgdXNlIHZlY3RvciBvcGVyYXRpb25zPyAgT25lIGNvdWxkIGVhc2lseSBhcmd1ZSB0 aGF0IHRoZSBjb252ZXJzZSBpcwp0cnVlOiBubyBleGlzdGluZyBzb2Z0d2FyZSB1c2VzIHRoZSB2 ZWN0b3IgZXh0ZW5zaW9uIG5vdywgc28gbW9zdCBsaWtlbHkgYQpwcm9jZXNzIHdpbGwgbm90IGJl IHVzaW5nIGl0LgoKPiAKPiA+IEdpdmVuIHRoZSBzaXplIG9mIHRoZSB2ZWN0b3Igc3RhdGUgYW5k IHBvdGVudGlhbCBwb3dlciBhbmQgcGVyZm9ybWFuY2UKPiA+IGltcGxpY2F0aW9ucyBvZiBlbmFi bGluZyB0aGUgdmVjdG9yIGVuZ2luZSwgaXQgc2VlbXMgbGlrZSB0aGlzIHNob3VsZAo+ID4gdHJl YXRlZCBzaW1pbGFybHkgdG8gSW50ZWwgQU1YIG9uIHg4Ni4gIFRoZSBmdWxsIGRpc2N1c3Npb24g b2YgdGhhdCBpcwo+ID4gaGVyZToKPiA+Cj4gPiBodHRwczovL2xvcmUua2VybmVsLm9yZy9sa21s L0NBTENFVHJXMlFIYTJUTHZuVXVWeEFBaGVxY2JTWi01X1dSWHREU0FHY2JHOE4rZ3RkUS1Kc29B d1VJc1hvc04rQnFROXJCRVVnQHB1YmxpYy5nbWFuZS5vcmcvCj4gPgo+ID4gVGhlIGNvdmVyIGxl dHRlciBmb3IgcmVjZW50IEludGVsIEFNWCBwYXRjaGVzIGhhcyBhIHN1bW1hcnkgb2YgdGhlIHg4 Ngo+ID4gaW1wbGVtZW50YXRpb246Cj4gPgo+ID4gaHR0cHM6Ly9sb3JlLmtlcm5lbC5vcmcvbGtt bC8yMDIxMDgyNTE1NTQxMy4xOTY3My0xLWNoYW5nLnNlb2suYmFlQGludGVsLmNvbS8KPiA+Cj4g PiBJZiBSSVNDLVYgd2VyZSB0byBhZG9wdCBhIHNpbWlsYXIgYXBwcm9hY2gsIEkgdGhpbmsgdGhl IHNpZ25pZmljYW50Cj4gPiBwb2ludHMgYXJlOgo+ID4KPiA+ICAgMS4gQSBwcm9jZXNzIChvciB0 aHJlYWQpIG11c3Qgc3BlY2lmaWNhbGx5IHJlcXVlc3QgdGhlIGRlc2lyZSB0byB1c2UKPiA+IHZl Y3RvciBleHRlbnNpb25zIChwZXJoYXBzIHdpdGggc29tZSBuZXcgYXJjaF9wcmN0bCgpIEFQSSks Cj4gPgo+ID4gICAyLiBUaGUga2VybmVsIGlzIGZyZWUgdG8gZGVueSBwZXJtaXNzaW9uLCBwZXJo YXBzIGJhc2VkIG9uCj4gPiBhZG1pbmlzdHJhdGl2ZSBydWxlcyBvciBmb3Igb3RoZXIgcmVhc29u cywgYW5kCj4gPgo+ID4gICAzLiBJZiBhIHByb2Nlc3MgYXR0ZW1wdHMgdG8gdXNlIHZlY3RvciBl eHRlbnNpb25zIGJlZm9yZSBkb2luZyB0aGUKPiA+IGFib3ZlLCB0aGUgcHJvY2VzcyB3aWxsIGRp ZSBkdWUgdG8gYW4gaWxsZWdhbCBpbnN0cnVjdGlvbi4KPiAKPiBUaGFuayB5b3UgZm9yIHNoYXJp bmcgdGhpcywgYnV0IEkgYW0gbm90IHN1cmUgaWYgd2Ugc2hvdWxkIHRyZWF0Cj4gdmVjdG9yIGxp a2UgQU1YIG9uIHg4Ni4gSU1ITywgY29tcGlsZXIgbWlnaHQgZ2VuZXJhdGUgY29kZSB3aXRoIHZl Y3Rvcgo+IGluc3RydWN0aW9ucyBhdXRvbWF0aWNhbGx5IHNvbWVkYXksIG1heWJlIHdlIHNob3Vs ZCB0cmVhdCB2ZWN0b3IKPiBleHRlbnNpb25zIGxpa2Ugb3RoZXIgZXh0ZW5zaW9ucy4KPiBJZiB1 c2VyIGtub3dzIHRoZSB2ZWN0b3IgZXh0ZW5zaW9uIGlzIHN1cHBvcnRlZCBpbiB0aGlzIENQVSBh bmQgaGUKPiB3b3VsZCBsaWtlIHRvIHVzZSBpdCwgaXQgc2VlbXMgd2Ugc2hvdWxkIGxldCB1c2Vy IHVzZSBpdCBkaXJlY3RseSBqdXN0Cj4gbGlrZSBvdGhlciBleHRlbnNpb25zLgo+IElmIHVzZXIg ZG9uJ3Qga25vdyBpdCBleGlzdHMgb3Igbm90LCB1c2VyIHNob3VsZCB1c2UgdGhlIGxpYnJhcnkg QVBJCj4gdHJhbnNwYXJlbnRseSBhbmQgbGV0IGdsaWJjIG9yIG90aGVyIGxpYnJhcnkgZGVhbCB3 aXRoIGl0LiBUaGUgZ2xpYmMKPiBpZnVuYyBmZWF0dXJlIG9yIG11bHRpLWxpYiBzaG91bGQgYmUg YWJsZSB0byBjaG9vc2UgdGhlIGNvcnJlY3QKPiBpbXBsZW1lbnRhdGlvbi4KCldoYXQgbWFrZXMg bWUgdGhpbmsgdGhhdCB0aGUgdmVjdG9yIGV4dGVuc2lvbiBzaG91bGQgYmUgdHJlYXRlZCBsaWtl IEFNWCBpcwp0aGF0IHRoZXkgYm90aCAoMSkgaGF2ZSBhIHNpZ25pZmljYW50IGFtb3VudCBvZiBh cmNoaXRlY3R1cmFsIHN0YXRlLCBhbmQKKDIpIGxpa2VseSBoYXZlIGEgc2lnbmlmaWNhbnQgcG93 ZXIgYW5kL29yIGFyZWEgaW1wYWN0IG9uIChub24tZW11bGF0ZWQpCmRlc2lnbnMuCgpGb3IgZXhh bXBsZSwgSSB0aGluayBpdCBpcyBwb3NzaWJsZSwgbWF5YmUgZXZlbiBsaWtlbHksIHRoYXQgdmVj dG9yCmltcGxlbWVudGF0aW9ucyB3aWxsIGhhdmUgb25lIG9yIG1vcmUgb2YgdGhlIGZvbGxvd2lu ZyBiZWhhdmlvcnM6CgogIDEuIEEgc2luZ2xlIHZlY3RvciB1bml0IHNoYXJlZCBhbW9uZyB0d28g b3IgbW9yZSBoYXJ0cywKCiAgMi4gQWRkaXRpb25hbCBwb3dlciBjb25zdW1wdGlvbiB3aGVuIHRo ZSB2ZWN0b3IgdW5pdCBpcyBlbmFibGVkIGFuZCBpZGxlCnZlcnN1cyBub3QgYmVpbmcgZW5hYmxl ZCBhdCBhbGwsCgogIDMuIEZvciBhIHN5c3RlbSB3aGljaCBzdXBwb3J0cyB2YXJpYWJsZSBvcGVy YXRpbmcgZnJlcXVlbmN5LCBhIHJlZHVjdGlvbgppbiB0aGUgbWF4aW11bSBmcmVxdWVuY3kgd2hl biB0aGUgdmVjdG9yIHVuaXQgaXMgZW5hYmxlZCwgYW5kL29yCgogIDQuIFRoZSBpbmFiaWxpdHkg dG8gZW50ZXIgbG93IHBvd2VyIHN0YXRlcyBhbmQvb3IgZGVsYXlzIHRvIGxvdyBwb3dlcgpzdGF0 ZXMgdHJhbnNpdGlvbnMgd2hlbiB0aGUgdmVjdG9yIHVuaXQgaXMgZW5hYmxlZC4KCk5vbmUgb2Yg dGhlIGFib3ZlIGNvbnN0cmFpbnRzIGFwcGx5IHRvIG1vcmUgb3JkaW5hcnkgZXh0ZW5zaW9ucyBs aWtlCmNvbXByZXNzZWQgb3IgdGhlIHZhcmlvdXMgYml0IG1hbmlwdWxhdGlvbiBleHRlbnNpb25z LgoKVGhlIGRpc2N1c3Npb24gSSBsaW5rZWQgdG8gaGFzIHNvbWUgd2VsbCByZWFzb25lZCBhcmd1 bWVudHMgb24gd2h5CnN1YnN0YW50aWFsIGV4dGVuc2lvbnMgc2hvdWxkIGhhdmUgYSBtZWNoYW5p c20gdG8gcmVxdWVzdCB1c2luZyB0aGVtIGJ5CnVzZXIgc3BhY2UuICBUaGUgZGlzY3Vzc2lvbiB3 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linux-kernel@vger.kernel.org On Tue, Sep 28, 2021 at 10:56:52PM +0800, Greentime Hu wrote: > Darius Rad 於 2021年9月13日 週一 下午8:21寫道： > > > > On 9/8/21 1:45 PM, Greentime Hu wrote: > > > This patch adds task switch support for vector. It supports partial lazy > > > save and restore mechanism. It also supports all lengths of vlen. > > > > > > [guoren@linux.alibaba.com: First available porting to support vector > > > context switching] > > > [nick.knight@sifive.com: Rewrite vector.S to support dynamic vlen, xlen and > > > code refine] > > > [vincent.chen@sifive.co: Fix the might_sleep issue in vstate_save, > > > vstate_restore] > > > Co-developed-by: Nick Knight > > > Signed-off-by: Nick Knight > > > Co-developed-by: Guo Ren > > > Signed-off-by: Guo Ren > > > Co-developed-by: Vincent Chen > > > Signed-off-by: Vincent Chen > > > Signed-off-by: Greentime Hu > > > --- > > > arch/riscv/include/asm/switch_to.h | 66 +++++++++++++++++++++++ > > > arch/riscv/kernel/Makefile | 1 + > > > arch/riscv/kernel/process.c | 38 ++++++++++++++ > > > arch/riscv/kernel/vector.S | 84 ++++++++++++++++++++++++++++++ > > > 4 files changed, 189 insertions(+) > > > create mode 100644 arch/riscv/kernel/vector.S > > > > > > diff --git a/arch/riscv/include/asm/switch_to.h b/arch/riscv/include/asm/switch_to.h > > > index ec83770b3d98..de0573dad78f 100644 > > > --- a/arch/riscv/include/asm/switch_to.h > > > +++ b/arch/riscv/include/asm/switch_to.h > > > @@ -7,10 +7,12 @@ > > > #define _ASM_RISCV_SWITCH_TO_H > > > > > > #include > > > +#include > > > #include > > > #include > > > #include > > > #include > > > +#include > > > > > > #ifdef CONFIG_FPU > > > extern void __fstate_save(struct task_struct *save_to); > > > @@ -68,6 +70,68 @@ static __always_inline bool has_fpu(void) { return false; } > > > #define __switch_to_fpu(__prev, __next) do { } while (0) > > > #endif > > > > > > +#ifdef CONFIG_VECTOR > > > +extern bool has_vector; > > > +extern unsigned long riscv_vsize; > > > +extern void __vstate_save(struct __riscv_v_state *save_to, void *datap); > > > +extern void __vstate_restore(struct __riscv_v_state *restore_from, void *datap); > > > + > > > +static inline void __vstate_clean(struct pt_regs *regs) > > > +{ > > > + regs->status = (regs->status & ~(SR_VS)) | SR_VS_CLEAN; > > > +} > > > + > > > +static inline void vstate_off(struct task_struct *task, > > > + struct pt_regs *regs) > > > +{ > > > + regs->status = (regs->status & ~SR_VS) | SR_VS_OFF; > > > +} > > > + > > > +static inline void vstate_save(struct task_struct *task, > > > + struct pt_regs *regs) > > > +{ > > > + if ((regs->status & SR_VS) == SR_VS_DIRTY) { > > > + struct __riscv_v_state *vstate = &(task->thread.vstate); > > > + > > > + __vstate_save(vstate, vstate->datap); > > > + __vstate_clean(regs); > > > + } > > > +} > > > + > > > +static inline void vstate_restore(struct task_struct *task, > > > + struct pt_regs *regs) > > > +{ > > > + if ((regs->status & SR_VS) != SR_VS_OFF) { > > > + struct __riscv_v_state *vstate = &(task->thread.vstate); > > > + > > > + /* Allocate space for vector registers. */ > > > + if (!vstate->datap) { > > > + vstate->datap = kzalloc(riscv_vsize, GFP_ATOMIC); > > > + vstate->size = riscv_vsize; > > > + } > > > + __vstate_restore(vstate, vstate->datap); > > > + __vstate_clean(regs); > > > + } > > > +} > > > + > > > +static inline void __switch_to_vector(struct task_struct *prev, > > > + struct task_struct *next) > > > +{ > > > + struct pt_regs *regs; > > > + > > > + regs = task_pt_regs(prev); > > > + if (unlikely(regs->status & SR_SD)) > > > + vstate_save(prev, regs); > > > + vstate_restore(next, task_pt_regs(next)); > > > +} > > > + > > > +#else > > > +#define has_vector false > > > +#define vstate_save(task, regs) do { } while (0) > > > +#define vstate_restore(task, regs) do { } while (0) > > > +#define __switch_to_vector(__prev, __next) do { } while (0) > > > +#endif > > > + > > > extern struct task_struct *__switch_to(struct task_struct *, > > > struct task_struct *); > > > > > > @@ -77,6 +141,8 @@ do { \ > > > struct task_struct *__next = (next); \ > > > if (has_fpu()) \ > > > __switch_to_fpu(__prev, __next); \ > > > + if (has_vector) \ > > > + __switch_to_vector(__prev, __next); \ > > > ((last) = __switch_to(__prev, __next)); \ > > > } while (0) > > > > > > diff --git a/arch/riscv/kernel/Makefile b/arch/riscv/kernel/Makefile > > > index 3397ddac1a30..344078080839 100644 > > > --- a/arch/riscv/kernel/Makefile > > > +++ b/arch/riscv/kernel/Makefile > > > @@ -40,6 +40,7 @@ obj-$(CONFIG_MMU) += vdso.o vdso/ > > > > > > obj-$(CONFIG_RISCV_M_MODE) += traps_misaligned.o > > > obj-$(CONFIG_FPU) += fpu.o > > > +obj-$(CONFIG_VECTOR) += vector.o > > > obj-$(CONFIG_SMP) += smpboot.o > > > obj-$(CONFIG_SMP) += smp.o > > > obj-$(CONFIG_SMP) += cpu_ops.o > > > diff --git a/arch/riscv/kernel/process.c b/arch/riscv/kernel/process.c > > > index 03ac3aa611f5..0b86e9e531c9 100644 > > > --- a/arch/riscv/kernel/process.c > > > +++ b/arch/riscv/kernel/process.c > > > @@ -95,6 +95,16 @@ void start_thread(struct pt_regs *regs, unsigned long pc, > > > */ > > > fstate_restore(current, regs); > > > } > > > + > > > + if (has_vector) { > > > + regs->status |= SR_VS_INITIAL; > > > + /* > > > + * Restore the initial value to the vector register > > > + * before starting the user program. > > > + */ > > > + vstate_restore(current, regs); > > > + } > > > + > > > > So this will unconditionally enable vector instructions, and allocate > > memory for vector state, for all processes, regardless of whether vector > > instructions are used? > > > > Hi Darius, > > Yes, it will enable vector if has_vector() is true. The reason that we > choose to enable and allocate memory for user space program is because > we also implement some common functions in the glibc such as memcpy > vector version and it is called very often by every process. So that > we assume if the user program is running in a CPU with vector ISA > would like to use vector by default. If we disable it by default and > make it trigger the illegal instruction, that might be a burden since > almost every process will use vector glibc memcpy or something like > that. Do you have any evidence to support the assertion that almost every process would use vector operations? One could easily argue that the converse is true: no existing software uses the vector extension now, so most likely a process will not be using it. > > > Given the size of the vector state and potential power and performance > > implications of enabling the vector engine, it seems like this should > > treated similarly to Intel AMX on x86. The full discussion of that is > > here: > > > > https://lore.kernel.org/lkml/CALCETrW2QHa2TLvnUuVxAAheqcbSZ-5_WRXtDSAGcbG8N+gtdQ-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org/ > > > > The cover letter for recent Intel AMX patches has a summary of the x86 > > implementation: > > > > https://lore.kernel.org/lkml/20210825155413.19673-1-chang.seok.bae@intel.com/ > > > > If RISC-V were to adopt a similar approach, I think the significant > > points are: > > > > 1. A process (or thread) must specifically request the desire to use > > vector extensions (perhaps with some new arch_prctl() API), > > > > 2. The kernel is free to deny permission, perhaps based on > > administrative rules or for other reasons, and > > > > 3. If a process attempts to use vector extensions before doing the > > above, the process will die due to an illegal instruction. > > Thank you for sharing this, but I am not sure if we should treat > vector like AMX on x86. IMHO, compiler might generate code with vector > instructions automatically someday, maybe we should treat vector > extensions like other extensions. > If user knows the vector extension is supported in this CPU and he > would like to use it, it seems we should let user use it directly just > like other extensions. > If user don't know it exists or not, user should use the library API > transparently and let glibc or other library deal with it. The glibc > ifunc feature or multi-lib should be able to choose the correct > implementation. What makes me think that the vector extension should be treated like AMX is that they both (1) have a significant amount of architectural state, and (2) likely have a significant power and/or area impact on (non-emulated) designs. For example, I think it is possible, maybe even likely, that vector implementations will have one or more of the following behaviors: 1. A single vector unit shared among two or more harts, 2. Additional power consumption when the vector unit is enabled and idle versus not being enabled at all, 3. For a system which supports variable operating frequency, a reduction in the maximum frequency when the vector unit is enabled, and/or 4. The inability to enter low power states and/or delays to low power states transitions when the vector unit is enabled. None of the above constraints apply to more ordinary extensions like compressed or the various bit manipulation extensions. The discussion I linked to has some well reasoned arguments on why substantial extensions should have a mechanism to request using them by user space. The discussion was in the context of Intel AMX, but applies to further x86 extensions, and I think should also apply to similar extensions on RISC-V, like vector here.