From: Catalin Marinas <catalin.marinas@arm.com>
To: Peter Collingbourne <pcc@google.com>
Cc: Vincenzo Frascino <vincenzo.frascino@arm.com>,
Will Deacon <will@kernel.org>,
Andrey Konovalov <andreyknvl@gmail.com>,
Evgenii Stepanov <eugenis@google.com>,
linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH] arm64: mte: avoid clearing PSTATE.TCO on entry unless necessary
Date: Tue, 5 Oct 2021 17:46:09 +0100 [thread overview]
Message-ID: <YVyBUVpA3CtTiZ6r@arm.com> (raw)
In-Reply-To: <20210929194525.3252555-1-pcc@google.com>
On Wed, Sep 29, 2021 at 12:45:24PM -0700, Peter Collingbourne wrote:
> diff --git a/arch/arm64/kernel/entry.S b/arch/arm64/kernel/entry.S
> index 2f69ae43941d..85ead6bbb38e 100644
> --- a/arch/arm64/kernel/entry.S
> +++ b/arch/arm64/kernel/entry.S
> @@ -269,7 +269,28 @@ alternative_else_nop_endif
> .else
> add x21, sp, #PT_REGS_SIZE
> get_current_task tsk
> + ldr x0, [tsk, THREAD_SCTLR_USER]
> .endif /* \el == 0 */
> +
> + /*
> + * Re-enable tag checking (TCO set on exception entry). This is only
> + * necessary if MTE is enabled in either the kernel or the userspace
> + * task in synchronous mode. With MTE disabled in the kernel and
> + * disabled or asynchronous in userspace, tag check faults (including in
> + * uaccesses) are not reported, therefore there is no need to re-enable
> + * checking. This is beneficial on microarchitectures where re-enabling
> + * TCO is expensive.
> + */
> +#ifdef CONFIG_ARM64_MTE
> +alternative_cb kasan_hw_tags_enable
> + tbz x0, #SCTLR_EL1_TCF0_SHIFT, 1f
> +alternative_cb_end
> +alternative_if ARM64_MTE
> + SET_PSTATE_TCO(0)
> +alternative_else_nop_endif
> +1:
> +#endif
I think we can get here from an interrupt as well. Can we guarantee that
the sctlr_user is valid? We are not always in a user process context.
Maybe only do the above checks if \el == 0, otherwise just bracket it
with kasan_hw_tags_enable.
--
Catalin
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2021-10-05 16:47 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-09-29 19:45 [PATCH] arm64: mte: avoid clearing PSTATE.TCO on entry unless necessary Peter Collingbourne
2021-10-05 16:46 ` Catalin Marinas [this message]
2021-10-05 19:08 ` Peter Collingbourne
2021-10-07 10:20 ` Mark Rutland
2021-11-05 20:18 ` Peter Collingbourne
2021-11-08 11:01 ` Mark Rutland
2021-11-10 22:07 ` Peter Collingbourne
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=YVyBUVpA3CtTiZ6r@arm.com \
--to=catalin.marinas@arm.com \
--cc=andreyknvl@gmail.com \
--cc=eugenis@google.com \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=pcc@google.com \
--cc=vincenzo.frascino@arm.com \
--cc=will@kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.