From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 78885C433F5 for ; Fri, 22 Oct 2021 11:23:27 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 51132610A1 for ; Fri, 22 Oct 2021 11:23:27 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232584AbhJVLZn (ORCPT ); Fri, 22 Oct 2021 07:25:43 -0400 Received: from mail.kernel.org ([198.145.29.99]:48270 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232539AbhJVLZn (ORCPT ); Fri, 22 Oct 2021 07:25:43 -0400 Received: by mail.kernel.org (Postfix) with ESMTPSA id 511CB60F8F; Fri, 22 Oct 2021 11:23:24 +0000 (UTC) Date: Fri, 22 Oct 2021 12:23:20 +0100 From: Catalin Marinas To: Mark Brown Cc: Will Deacon , Shuah Khan , Shuah Khan , Alan Hayward , Luis Machado , Salil Akerkar , Basant Kumar Dwivedi , Szabolcs Nagy , linux-arm-kernel@lists.infradead.org, linux-kselftest@vger.kernel.org Subject: Re: [PATCH v3 07/42] arm64/sve: Put system wide vector length information into structs Message-ID: References: <20211019172247.3045838-1-broonie@kernel.org> <20211019172247.3045838-8-broonie@kernel.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20211019172247.3045838-8-broonie@kernel.org> Precedence: bulk List-ID: X-Mailing-List: linux-kselftest@vger.kernel.org On Tue, Oct 19, 2021 at 06:22:12PM +0100, Mark Brown wrote: > diff --git a/arch/arm64/include/asm/fpsimd.h b/arch/arm64/include/asm/fpsimd.h > index d164e2f35837..5a1f79a4a500 100644 > --- a/arch/arm64/include/asm/fpsimd.h > +++ b/arch/arm64/include/asm/fpsimd.h > @@ -77,10 +77,6 @@ extern void sve_kernel_enable(const struct arm64_cpu_capabilities *__unused); > > extern u64 read_zcr_features(void); > > -extern int __ro_after_init sve_max_vl; > -extern int __ro_after_init sve_max_virtualisable_vl; > -extern __ro_after_init DECLARE_BITMAP(sve_vq_map, SVE_VQ_MAX); > - > /* > * Helpers to translate bit indices in sve_vq_map to VQ values (and > * vice versa). This allows find_next_bit() to be used to find the [...] > @@ -139,11 +151,63 @@ static inline void sve_user_enable(void) [...] > +static inline int sve_max_virtualisable_vl(void) > +{ > + return vec_max_virtualisable_vl(ARM64_VEC_SVE); > +} With this change, sve_max_virtualisable_vl() is only defined if CONFIG_ARM64_SVE is enabled but it's still referenced from kvm_arm_init_sve() and kvm_vcpu_finalize_sve(), so the build fails if SVE is disabled. > +static struct vl_config vl_config[ARM64_VEC_MAX]; > + > +static int get_default_vl(enum vec_type type) > +{ > + return READ_ONCE(vl_config[type].__default_vl); > +} > > static int get_sve_default_vl(void) > { > - return READ_ONCE(__sve_default_vl); > + return get_default_vl(ARM64_VEC_SVE); > } > > #ifdef CONFIG_ARM64_SVE I think after patch 9 I think I also get a warning on get_sve_default_vl() defined but not used when SVE is disabled. Maybe move the #ifdef higher but also make these static inline. > > -static void set_sve_default_vl(int val) > +static void set_default_vl(enum vec_type type, int val) > { > - WRITE_ONCE(__sve_default_vl, val); > + WRITE_ONCE(vl_config[type].__default_vl, val); > } Same here, it should probably be static inline. > > -/* Maximum supported vector length across all CPUs (initially poisoned) */ > -int __ro_after_init sve_max_vl = SVE_VL_MIN; > -int __ro_after_init sve_max_virtualisable_vl = SVE_VL_MIN; > - > -/* > - * Set of available vector lengths, > - * where length vq encoded as bit __vq_to_bit(vq): > - */ > -__ro_after_init DECLARE_BITMAP(sve_vq_map, SVE_VQ_MAX); > -/* Set of vector lengths present on at least one cpu: */ > -static __ro_after_init DECLARE_BITMAP(sve_vq_partial_map, SVE_VQ_MAX); > +static void set_sve_default_vl(int val) > +{ > + set_default_vl(ARM64_VEC_SVE, val); > +} And here. -- Catalin From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 09868C433F5 for ; Fri, 22 Oct 2021 11:24:47 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id C14F260F4F for ; Fri, 22 Oct 2021 11:24:46 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org C14F260F4F Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:Cc:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=NSuToCHZGWT/AEPU7ZSjQ/yyh1n4uMs4ypzVP6MJvaY=; b=Iwh2clOR00TZPX +ATvyBJgJJNdpO8acYhEbzVVUAz3Jx2mKRvQEffvB2mcDELIIfQO+1cY8g7BpvR6sFvsCZIOLR+Lo ifPb8qPC+/ZaTRbSEF/PHV3wBm3pisW+hyTNo3f2rOoZlH9dhgHrpzpDuuvd7bzcIEDuxAwE5kzYH 2zyLsItT9q7dQCRdv1lAXAwr5znUE/RKGPiflRKQC/ozhpxwtpZjnQVTbfs+Au+UsEgntP9lGR/78 +fyKi9pOIxmuiSF91qhn/C6mTsYt0cplczBAzJcXQhXeiqfffKB5M/FgwnXdXKXpJKwYf4dyyEbuo wX3b4Lj0ddl9QdUtbaSw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1mdse3-00AdTh-3l; Fri, 22 Oct 2021 11:23:31 +0000 Received: from mail.kernel.org ([198.145.29.99]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1mdsdy-00AdSg-Iz for linux-arm-kernel@lists.infradead.org; Fri, 22 Oct 2021 11:23:27 +0000 Received: by mail.kernel.org (Postfix) with ESMTPSA id 511CB60F8F; Fri, 22 Oct 2021 11:23:24 +0000 (UTC) Date: Fri, 22 Oct 2021 12:23:20 +0100 From: Catalin Marinas To: Mark Brown Cc: Will Deacon , Shuah Khan , Shuah Khan , Alan Hayward , Luis Machado , Salil Akerkar , Basant Kumar Dwivedi , Szabolcs Nagy , linux-arm-kernel@lists.infradead.org, linux-kselftest@vger.kernel.org Subject: Re: [PATCH v3 07/42] arm64/sve: Put system wide vector length information into structs Message-ID: References: <20211019172247.3045838-1-broonie@kernel.org> <20211019172247.3045838-8-broonie@kernel.org> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20211019172247.3045838-8-broonie@kernel.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20211022_042326_671176_402F4041 X-CRM114-Status: GOOD ( 20.30 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Tue, Oct 19, 2021 at 06:22:12PM +0100, Mark Brown wrote: > diff --git a/arch/arm64/include/asm/fpsimd.h b/arch/arm64/include/asm/fpsimd.h > index d164e2f35837..5a1f79a4a500 100644 > --- a/arch/arm64/include/asm/fpsimd.h > +++ b/arch/arm64/include/asm/fpsimd.h > @@ -77,10 +77,6 @@ extern void sve_kernel_enable(const struct arm64_cpu_capabilities *__unused); > > extern u64 read_zcr_features(void); > > -extern int __ro_after_init sve_max_vl; > -extern int __ro_after_init sve_max_virtualisable_vl; > -extern __ro_after_init DECLARE_BITMAP(sve_vq_map, SVE_VQ_MAX); > - > /* > * Helpers to translate bit indices in sve_vq_map to VQ values (and > * vice versa). This allows find_next_bit() to be used to find the [...] > @@ -139,11 +151,63 @@ static inline void sve_user_enable(void) [...] > +static inline int sve_max_virtualisable_vl(void) > +{ > + return vec_max_virtualisable_vl(ARM64_VEC_SVE); > +} With this change, sve_max_virtualisable_vl() is only defined if CONFIG_ARM64_SVE is enabled but it's still referenced from kvm_arm_init_sve() and kvm_vcpu_finalize_sve(), so the build fails if SVE is disabled. > +static struct vl_config vl_config[ARM64_VEC_MAX]; > + > +static int get_default_vl(enum vec_type type) > +{ > + return READ_ONCE(vl_config[type].__default_vl); > +} > > static int get_sve_default_vl(void) > { > - return READ_ONCE(__sve_default_vl); > + return get_default_vl(ARM64_VEC_SVE); > } > > #ifdef CONFIG_ARM64_SVE I think after patch 9 I think I also get a warning on get_sve_default_vl() defined but not used when SVE is disabled. Maybe move the #ifdef higher but also make these static inline. > > -static void set_sve_default_vl(int val) > +static void set_default_vl(enum vec_type type, int val) > { > - WRITE_ONCE(__sve_default_vl, val); > + WRITE_ONCE(vl_config[type].__default_vl, val); > } Same here, it should probably be static inline. > > -/* Maximum supported vector length across all CPUs (initially poisoned) */ > -int __ro_after_init sve_max_vl = SVE_VL_MIN; > -int __ro_after_init sve_max_virtualisable_vl = SVE_VL_MIN; > - > -/* > - * Set of available vector lengths, > - * where length vq encoded as bit __vq_to_bit(vq): > - */ > -__ro_after_init DECLARE_BITMAP(sve_vq_map, SVE_VQ_MAX); > -/* Set of vector lengths present on at least one cpu: */ > -static __ro_after_init DECLARE_BITMAP(sve_vq_partial_map, SVE_VQ_MAX); > +static void set_sve_default_vl(int val) > +{ > + set_default_vl(ARM64_VEC_SVE, val); > +} And here. -- Catalin _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel