From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E6345C433FE for ; Tue, 23 Nov 2021 07:38:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234028AbhKWHl4 (ORCPT ); Tue, 23 Nov 2021 02:41:56 -0500 Received: from muru.com ([72.249.23.125]:59222 "EHLO muru.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233737AbhKWHl4 (ORCPT ); Tue, 23 Nov 2021 02:41:56 -0500 Received: from localhost (localhost [127.0.0.1]) by muru.com (Postfix) with ESMTPS id 6489480F5; Tue, 23 Nov 2021 07:39:26 +0000 (UTC) Date: Tue, 23 Nov 2021 09:38:45 +0200 From: Tony Lindgren To: =?utf-8?B?UmFmYcWCIE1pxYJlY2tp?= Cc: Linus Walleij , Rob Herring , Andy Shevchenko , linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Florian Fainelli , bcm-kernel-feedback-list@broadcom.com, =?utf-8?B?UmFmYcWCIE1pxYJlY2tp?= Subject: Re: [PATCH 2/5] dt-bindings: pinctrl: brcm,ns-pinmux: extend example Message-ID: References: <20211118132152.15722-1-zajec5@gmail.com> <20211118132152.15722-3-zajec5@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20211118132152.15722-3-zajec5@gmail.com> Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Hi, 200* Rafał Miłecki [211118 13:30]: > @@ -83,6 +83,33 @@ examples: > reg = <0x1800c1c0 0x24>; > reg-names = "cru_gpio_control"; > > + pins { > + #address-cells = <1>; > + #size-cells = <0>; > + > + pin@4 { > + reg = <4>; > + label = "i2c_scl"; > + }; > + > + pin@5 { > + reg = <5>; > + label = "i2c_sda"; > + }; > + }; The reg property should indicate the hardware offset from the device base address. The reg values above for 4 and 5 seem to be indexed instead :) Please update to use real register offsets from the 0x1800c1c0 base instead. If a reg offset + bit offset are needed, the #address-cells or #pinctrl-cells can be used. The main problem using an index is that you need to keep it in sync between the dts and device driver. And if a new SoC variant adds an entry between the registers, you end up having to renumber the index. Regards, Tony From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 42AC4C433EF for ; Tue, 23 Nov 2021 07:40:13 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:Cc:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=ylwWNcmODd3EKle6GuqRnQHmNTk0HDGkEQ+wmODFJn0=; b=QvvfqZfAd/n6lm tw0c+negzZ+xzr44r/vIU1d42XruZ7vOC4ZSU6crOTZ5WHtGd9KV0mbJ6I2oB7t0fOKWLQecbolmv nX5mOPI1btkTtPRRoBmsifi5AzDzh1kab4YfJn87V3GFwA5QzYbwLnCeOJ3+D/EBGtID0HPsN+Axw J/ZmBEWbuH0fN7R4R8fwdX7c86yVcvF0KUAorjcqMs0S+l+0d+4913f1iXrkridkYzkbONP2iJOU0 NUi+4ilQxcL6d+DCKUNhBwmkAoqPx5Lo6TJteTedCE7PZnIyoxociZSOoVZKcA3vuAupK3ERuElQ0 JhwPGbgV4PuKthctj19A==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1mpQOF-0014Wf-L8; Tue, 23 Nov 2021 07:38:55 +0000 Received: from muru.com ([72.249.23.125]) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1mpQOC-0014Vi-1c for linux-arm-kernel@lists.infradead.org; Tue, 23 Nov 2021 07:38:53 +0000 Received: from localhost (localhost [127.0.0.1]) by muru.com (Postfix) with ESMTPS id 6489480F5; Tue, 23 Nov 2021 07:39:26 +0000 (UTC) Date: Tue, 23 Nov 2021 09:38:45 +0200 From: Tony Lindgren To: =?utf-8?B?UmFmYcWCIE1pxYJlY2tp?= Cc: Linus Walleij , Rob Herring , Andy Shevchenko , linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Florian Fainelli , bcm-kernel-feedback-list@broadcom.com, =?utf-8?B?UmFmYcWCIE1pxYJlY2tp?= Subject: Re: [PATCH 2/5] dt-bindings: pinctrl: brcm,ns-pinmux: extend example Message-ID: References: <20211118132152.15722-1-zajec5@gmail.com> <20211118132152.15722-3-zajec5@gmail.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20211118132152.15722-3-zajec5@gmail.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20211122_233852_173056_FC0DEE34 X-CRM114-Status: GOOD ( 11.51 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org SGksCgoyMDAqIFJhZmHFgiBNacWCZWNraSA8emFqZWM1QGdtYWlsLmNvbT4gWzIxMTExOCAxMzoz MF06Cj4gQEAgLTgzLDYgKzgzLDMzIEBAIGV4YW1wbGVzOgo+ICAgICAgICAgIHJlZyA9IDwweDE4 MDBjMWMwIDB4MjQ+Owo+ICAgICAgICAgIHJlZy1uYW1lcyA9ICJjcnVfZ3Bpb19jb250cm9sIjsK PiAgCj4gKyAgICAgICAgcGlucyB7Cj4gKyAgICAgICAgICAgICNhZGRyZXNzLWNlbGxzID0gPDE+ Owo+ICsgICAgICAgICAgICAjc2l6ZS1jZWxscyA9IDwwPjsKPiArCj4gKyAgICAgICAgICAgIHBp bkA0IHsKPiArICAgICAgICAgICAgICAgIHJlZyA9IDw0PjsKPiArICAgICAgICAgICAgICAgIGxh YmVsID0gImkyY19zY2wiOwo+ICsgICAgICAgICAgICB9Owo+ICsKPiArICAgICAgICAgICAgcGlu QDUgewo+ICsgICAgICAgICAgICAgICAgcmVnID0gPDU+Owo+ICsgICAgICAgICAgICAgICAgbGFi ZWwgPSAiaTJjX3NkYSI7Cj4gKyAgICAgICAgICAgIH07Cj4gKyAgICAgICAgfTsKClRoZSByZWcg cHJvcGVydHkgc2hvdWxkIGluZGljYXRlIHRoZSBoYXJkd2FyZSBvZmZzZXQgZnJvbSB0aGUgZGV2 aWNlIGJhc2UKYWRkcmVzcy4gVGhlIHJlZyB2YWx1ZXMgYWJvdmUgZm9yIDQgYW5kIDUgc2VlbSB0 byBiZSBpbmRleGVkIGluc3RlYWQgOikKUGxlYXNlIHVwZGF0ZSB0byB1c2UgcmVhbCByZWdpc3Rl ciBvZmZzZXRzIGZyb20gdGhlIDB4MTgwMGMxYzAgYmFzZQppbnN0ZWFkLiBJZiBhIHJlZyBvZmZz ZXQgKyBiaXQgb2Zmc2V0IGFyZSBuZWVkZWQsIHRoZSAjYWRkcmVzcy1jZWxscyBvcgojcGluY3Ry bC1jZWxscyBjYW4gYmUgdXNlZC4KClRoZSBtYWluIHByb2JsZW0gdXNpbmcgYW4gaW5kZXggaXMg dGhhdCB5b3UgbmVlZCB0byBrZWVwIGl0IGluIHN5bmMKYmV0d2VlbiB0aGUgZHRzIGFuZCBkZXZp Y2UgZHJpdmVyLiBBbmQgaWYgYSBuZXcgU29DIHZhcmlhbnQgYWRkcyBhbiBlbnRyeQpiZXR3ZWVu IHRoZSByZWdpc3RlcnMsIHlvdSBlbmQgdXAgaGF2aW5nIHRvIHJlbnVtYmVyIHRoZSBpbmRleC4K ClJlZ2FyZHMsCgpUb255CgoKX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19f X19fX19fX18KbGludXgtYXJtLWtlcm5lbCBtYWlsaW5nIGxpc3QKbGludXgtYXJtLWtlcm5lbEBs aXN0cy5pbmZyYWRlYWQub3JnCmh0dHA6Ly9saXN0cy5pbmZyYWRlYWQub3JnL21haWxtYW4vbGlz dGluZm8vbGludXgtYXJtLWtlcm5lbAo=