From: Andrew Lunn <andrew@lunn.ch>
To: Wells Lu <wellslutw@gmail.com>
Cc: davem@davemloft.net, kuba@kernel.org, robh+dt@kernel.org,
netdev@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, p.zabel@pengutronix.de,
wells.lu@sunplus.com, vincent.shih@sunplus.com
Subject: Re: [PATCH net-next v3 0/2] This is a patch series for pinctrl driver for Sunplus SP7021 SoC.
Date: Tue, 30 Nov 2021 21:17:57 +0100 [thread overview]
Message-ID: <YaaG9V2c/DL11GJC@lunn.ch> (raw)
In-Reply-To: <1638266572-5831-1-git-send-email-wellslutw@gmail.com>
On Tue, Nov 30, 2021 at 06:02:50PM +0800, Wells Lu wrote:
> Sunplus SP7021 is an ARM Cortex A7 (4 cores) based SoC. It integrates
> many peripherals (ex: UART, I2C, SPI, SDIO, eMMC, USB, SD card and
> etc.) into a single chip. It is designed for industrial control
> applications.
The subject line is wrong again. This has nothing to do with a pin
controller.
Andrew
next prev parent reply other threads:[~2021-11-30 20:18 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-11-30 10:02 [PATCH net-next v3 0/2] This is a patch series for pinctrl driver for Sunplus SP7021 SoC Wells Lu
2021-11-30 10:02 ` [PATCH net-next v3 1/2] devicetree: bindings: net: Add bindings doc for Sunplus SP7021 Wells Lu
2021-12-01 1:56 ` Andrew Lunn
2021-12-01 7:02 ` Wells Lu 呂芳騰
2021-11-30 10:02 ` [PATCH net-next v3 2/2] net: ethernet: Add driver " Wells Lu
2021-11-30 13:51 ` kernel test robot
2021-11-30 13:51 ` kernel test robot
2021-12-01 3:30 ` Andrew Lunn
2021-12-02 11:20 ` Wells Lu 呂芳騰
2021-12-02 13:04 ` Andrew Lunn
2021-12-02 18:46 ` Wells Lu 呂芳騰
2021-12-02 19:03 ` Andrew Lunn
2021-12-03 1:36 ` Wells Lu 呂芳騰
2021-11-30 20:17 ` Andrew Lunn [this message]
2021-12-01 1:42 ` [PATCH net-next v3 0/2] This is a patch series for pinctrl driver for Sunplus SP7021 SoC Wells Lu 呂芳騰
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