From: Mark Brown <broonie@kernel.org>
To: Dinh Nguyen <dinguyen@kernel.org>
Cc: devicetree@vger.kernel.org, robh+dt@kernel.org, p.yadav@ti.com
Subject: Re: [PATCHv2 1/3] dt-bindings: spi: cadence-quadspi: document "cdns,qspi-nor-ver-00-10"
Date: Fri, 3 Dec 2021 18:18:56 +0000 [thread overview]
Message-ID: <YapfkGNetHhA0Bws@sirena.org.uk> (raw)
In-Reply-To: <20211203181714.3138611-1-dinguyen@kernel.org>
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On Fri, Dec 03, 2021 at 12:17:12PM -0600, Dinh Nguyen wrote:
> The QSPI controller on Intel's SoCFPGA platform does not implement the
> CQSPI_REG_WR_COMPLETION_CTRL register, thus a write to this register
> results in a crash.
This is the third copy of this you've sent today with no differences
I've spotted between them - what's the story here?
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next prev parent reply other threads:[~2021-12-03 18:19 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-12-03 18:17 [PATCHv2 1/3] dt-bindings: spi: cadence-quadspi: document "cdns,qspi-nor-ver-00-10" Dinh Nguyen
2021-12-03 18:17 ` [PATCHv2 2/3] ARM: dts: socfpga: change qspi to "cdns,qspi-nor-ver-00-10" Dinh Nguyen
2021-12-03 18:17 ` [PATCH 3/3] spi: cadence-quadspi: change socfpga-qspi " Dinh Nguyen
2021-12-03 18:18 ` Mark Brown [this message]
2021-12-03 19:05 ` [PATCHv2 1/3] dt-bindings: spi: cadence-quadspi: document "cdns,qspi-nor-ver-00-10" Dinh Nguyen
2021-12-06 10:22 ` Pratyush Yadav
2021-12-08 23:45 ` Dinh Nguyen
2021-12-13 20:48 ` Rob Herring
2021-12-13 21:21 ` Dinh Nguyen
2021-12-14 20:05 ` Pratyush Yadav
2021-12-15 15:36 ` Dinh Nguyen
2021-12-16 18:58 ` Pratyush Yadav
-- strict thread matches above, loose matches on Subject: below --
2021-12-03 17:32 Dinh Nguyen
2021-12-03 14:01 Dinh Nguyen
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